RAM of any size and kind in your EFLX® array
(or custom accelerator logic)
Many applications like DSP benefit from blocks of RAM distributed in the array.
Of course it is possible to attach RAM to the external I/O pins of the array.
You can also have array embedded within the array! Each EFLX4K core has >1000 interface pins. When multiple cores are arrayed, the pins that face inward are available to control block any kind of RAM using our novel RAMLinx™ interconnect.
Any amount and kind of RAM can be inserted between cores: single or dual port, x16/x32/x64/..., ECC/parity/neither, and optional MBIST. The EFLX compiler can map your RTL onto the RAM you want to configure in the EFLX array (and to RAM external to the array).
A specific example is shown below for our soon-to-be-taped-out 28nm validation chip: here we have four EFLX cores with dual port RAM embedded horizontally and vertically, a total of 108Kbits. This particular example was chosen to provide BRAM of the sort found in FPGAs in the same rough ratio of RAM:Logic as typically found in FPGAs -- customers have requested this because they find this ratio of logic-to-RAM is best for many accelerator algorithms they wish to use on eFPGA.
CLICK HERE for a detailed app note on Connecting RAMS with EFLX Array & we have several architecture/applications engineers who can work with you to build the exact array with the exact RAMs your application requires.
We can do the same thing with custom accelerators, say matrix multipliers or floating point, and the EFLX Compiler can provide software support for them.