EFLX eFPGA is Compatible with Most Metal Stacks
FPGA chips typically use the maximum number of metal layers because of the traditional mesh interconnect.
Flex Logix uses a new, patented interconnect which is almost twice as dense as the traditional mesh AND uses many fewer metal layers.
EFLX eFPGA uses 6-7 metal layers for our 16nm IP, 6 metal layers for our 28nm IP and 5 metal layers for our 40nm IP. This means we are compatible with almost all metal stacks, whereas IP from our competitors use many more metal layers making them compatible with few metal stacks.
Dense, Portable, Scalable Silicon-Proven eFPGA GDS
Get the details here: White Paper on eFPGA IP Density, Portability and Scalability.
Customers want eFPGA IP GDS that is
- dense (more logic in less are than other eFPGA)
- works on the specific foundry/process node/variation that they have chosen
- works with the metal stack they have chosen
- the size they want (and with the options they want)
- silicon proven so they know it will work in their chip
Only Flex Logix can do this, currently across 7 process node/variation combinations and dozens of metal stacks for each, in sizes from 100 LUTs to 200K LUTs with options for DSP and RAM, all using a Silicon Proven EFLX IP core GDS which is UNCHANGED from the one proven on our validation chip.
Other eFPGA vendors cannot.
Vendors who generate eFPGA derived from their FPGA chips have to do full-custom design changes to move from one process variant to another (e.g. 16X to 16X+) and even to support most metal stacks. These changes require multiple months and mean the GDS they deliver is different from what is in their FPGA chip. Same for different array sizes.
Vendors who generate eFPGA from Soft IP have multiple array sizes: validating one doesn't proven the others. And they use standard cells with traditional FPGA interconnect, so their density is 1/2-1/3.
The reasons Flex Logix can deliver silicon proven, high density, scalable arrays over incremental process variations? Multiple inventions and innovations:
- a patented interconnect which is twice as area-efficient as traditional FPGA mesh interconnect AND which requires many fewer metal layers, enabling compatibility with most metal stacks
- a tiling approach where a single EFLX core is a complete eFPGA, but when abutted, a top-layer of interconnect is formed, without touching the GDS, to extend the eFPGA interconnect across arrays of many sizes up to 7x7
- 6-input-LUTs which get higher logic density and higher performance
- standard cells which enable rapid implementation and are GDS-compatible across incremental process variations (e.g. X/X+/X++): our patented interconnect makes up for the density that standard cells lose, so we still match the density of eFPGA from FPGA chips
- Validation chips in every process node of at least a 2x2 array proving out the top-level interconnects that enable arrays up to 7x7. Validation chips are designed with on-chip high speed RAM, PLL and PVT monitors so performance can be verified over -40C to +125C and over the full voltage range.