DSP acceleration application examples

The EFLX DSP acceleration block is a MAC optimized for 22-bit real and 11-bit complex (11-bit real, 11-bit imaginary) signal processing operating at up to 450MegaSamples/second worst case in TSMC 28HPM/HPC.  The pre-adder is 22 bits, the multiplier is 22-bits and the accumulator is 48-bits.

In an EFLX4K DSP core, there are 40 of these blocks. They can be pipelined and they can be concatenated to implement a wide range of DSP functions.  Shown below are numerous examples: 1st the math, 2nd the Verilog code, 3rd the high level data flow diagram and 4th a mapping onto the EFLX DSP architecture. More details are available in the EFLX DSP user's guide, available under NDA. A DSP Overview brief is available: click here for the PDF. The EFLX Compiler maps DSP RTL into the EFLX array and is available for evaluation to qualified customers.

In a TSMC 40ULP/LP EFLX100 DSP core, there are 2 of these blocks, functionally identical to EFLX4K.  

10-tap 22-bit Symmetric FIR filter

This maps onto 5 DSP blocks and runs at 450 Megasamples/second (SS, Vj=0.81V, 125C) in TSMC28HPM/HPC.

40-tap 22-bit Non-Symmetric FIR Filter

This maps onto 40 DSP blocks and operates at 212 Megasamples/second (SS, Vj=0.81V, T=125C) in TSMC28HPM/HPC.

Radix-2 Butterfly for Fast Fourier Transform (FFT)

This maps onto 2 DSP blocks and runs at 172 Megasamples/second (SS, Vj=0.81V, T=125C) in TSMC28HPM/HPC.

22-bit Complex Multiply (22-bit real, 22-bit imaginary)

This maps onto 3 DSP blocks and runs at 383 Megasamples/second (SS, 0.81V, 125C) in TSMC28HPM/HPC.

Wide 43-bit Real Multiplication

This maps onto 4 DSP blocks and operates at 370 Megasamples/second (SS, 0.81V, 125C) in TSMC28HPM/HPC.

Much more is possible. Contact us for more details under NDA.  We can help you with your specific application.

Contact us to get more information under NDA and/or for us to help you map your DSP application into the EFLX array to achieve your performance, power and cost objectives.