The proven EFLX Compiler is adding a Graphical User Interface based on customer demand.

Phase 1, the Timing Analyzer Module, is available now in our production EFLX Compiler release available for Software Evaluation License.


Our new timing analyzer module allows you to see a histogram of all timing nets, then for each histogram bar to see the nets and then drill down into each net to see the stage by stage timing.  This level of timing information aids in determining how to optimize your RTL for improving critical path worst case performance.  

Timing is computed based on output files from Tempus/PrimeTime which describe every timing path through the EFLX core/array.  Timing is available for each process node and for multiple corners for each process node (varying process conditions and voltages, not just worst case conditions).

Contact us for a demo and for a software evaluation license to try on your RTL:

Below are some details.

1st screen shows the 7 corners available for the TSMC 16FFC process.  An EDIF netlist can be selected and a corner can be selected for optimizing place & route.  Timing corners are available for all of the nominal voltages that TSMC supports: currently the 0.8V Tj nominal corners are populated (+/- 10%) and 1V corners for closing hold times.  In the example below, an 8K LUT design will be placed and routed with timing optimized for SS, 0.72V and 125C.

1 GUI launch.png

After place and route, a timing histogram is generated showing the number of critical paths at each speed.  The worst case performance for this example is 510.5MHz or 1959ps.  In the GUI, using the cursor, the rightmost histogram bar was selected (1900-2000ps): the pop-up window shows there are two paths in this histogram.

2 GUI Histogram.png

Then, in this example, the 1959ps path is selected in the first pop-up window, which generates a 2nd pop-up window (see below) showing the 5% slowest paths in the logic cone of this path.  Using this, a designer can see if one path is a lot worse than the others orin there a lot of similar paths.

3 GUI Startpoint-to-endpoint.png

Then, drilling down further, the designer can look at any of the paths in the logic cone (in the example below the 1946ps path is selected in the middle pop-up box).  Once a path is selected, the designer can see every stage from the output of one flip flop through the various logic and net delays that make up the total path delay.  

These data are based on silicon-sign-off data from Cadence Tempus, using TSMC cell libraries (CCS), wire load models (QRC), in the TSMC sign-off corners (e.g. SSGNP 0.72V, -40C RCworst-Ccworst-T, AOCV) following TSMC timing sign-off guidelines.  The database of timing reports and SDF timing annotation is then parsed by the EFLX Compiler to perform timing-analysis on your design in each corner.  This rigorous ASIC timing signoff method ensures your RTL running on the EFLX array will meet the EFLX Compiler timing the same way you designed your ASIC to meeting timing under worst-case conditions.  Unlike other FPGA companies, no timing margins or derates needs to be added to our timing-analysis reports because we use the same methodology you do for the rest of your chip.

These timing tools can allow the designer to gather information which may allow them to optimize the RTL to improve performance.  In a future phase of the GUI, the physical graph of the path through the array will also be observable. 

These timing tools can allow the designer to gather information which may allow them to optimize the RTL to improve performance.  In a future phase of the GUI, the physical graph of the path through the array will also be observable. 

floor planner.png


The 2nd phase of GUI release will add a mapper and floor planner - this will be in Q4.



graphical path tracer.png


The 3rd phase of the GUI release will add I/O specification, graphical path-tracer, power estimator and logic analyzer/debugger capabilities.  This will be in Q4 or Q1/2018.









Synplify: this widely used Synopsys tool takes your netlist/RTL and breaks it down into primitives in an EDIF format, which feeds into the EFLX Compiler.

EFLX™ Compiler:

  1. Input your RTL to see the resources required: # LUTs/Cores, DSP blocks and RAM.
  2. Configure your EFLX array: select the number and type of EFLX cores, the clocks, the I/O configuration connecting the array to the SoC, and the type and amount of Block RAM.
  3. Input your RTL with your configured array to determine the worst case path and frequency for your target process.
  4. Generate the bit file (bit stream) that programs the EFLX array in the SoC to execute your RTL.

The EFLX Compiler is now in use at customers for designs and evaluation.

We can demonstrate our tools by Web-ex and run RTL for a customer, if they wish..  

Here is a video demonstration of the key steps in compiling an RTL design for EFLX embedded FPGA to determine performance and LUT count.  (the timing files vary by process node).

For qualified customers we can provide free evaluation licenses.  Contact us at

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