New EFLX1K eFPGA Core Optimizes Area for 40-180nm Applications

Based on gen2 architecture for high density & speed

Our customers with applications such as IoT and MCU on 40-180nm nodes have different needs:  the amount of reconfigurable logic required is less and area is very important.  Even in an EFPX eFPGA with XFLX™ and ArrayLinx™ proprietary interconnects, interconnect takes up more area than programmable logic.  Our EFLX4K core for advanced nodes has extra interconnect to expand to very large arrays >200K LUTs.  In 40-180nm nodes the need for eFPGA is <20K LUTs.  So we have designed an optimized core architecture with less interconnect to save area.

The EFLX1K (~1000 LUT4 equivalents) has fewer interconnect resources, to reduce eFPGA area 10-20% versus the EFLX4K (measured in terms of total eFPGA area per thousand-LUTs), but can still array up to at least 4x4.  With EFLX1K arrays of 1K, 2K, 3K, 4K, 6K, 8K, 10K, 12K and 16K are possible giving a wide range of sizes with small increments of granularity.

Both Logic and DSP cores will be available and can be mixed interchangeably in arrays.  Below is a block diagram of the EFLX1K Logic core on the left and EFLX1K DSP core on the right.

2018 06 EFLX1K Logic and DSP cores.png

Each core has 368 inputs and 368 outputs (yellow).  The Logic core or tile has 900 LUT4 equivalents.  The DSP tiles replaces some of the LUTs: it has 10 DSP MACs, the same as in the EFLX4K, and 650 LUT4s.  The DSP MACs are arranged in two rows of 5: adjacent MACs can pipeline directly without needing to go through the interconnect network for even higher speed.  

The EFLX1K is fully supported by our EFLX Compiler software toolset.

This architecture can be implemented with or without power gating, as needed for the application (power gating gives more power management but cuts into the IR drop resulting in somewhat less performance).  The EFLX1K cores can be implemented in any process in 6-8 months.  

Download the EFLX1K Target Spec HERE.

Contact us at for further information.