New EFLX4K IO eFPGA Core for Very Wide, Fast Buses

512 bit bus, 1024 bit bus, 2048 bit bus or morE

In Networking ICs and Heterogeneous Processor SoCs, customers want to connect eFPGA to buses of 512 bits, 1024 bits, 2048 bits or more.  All of these pins will come into the eFPGA Array on one side.  And they may only need 4K or 8K LUT4s of logic capacity.  This is more I/O than our EFLX4K Logic core was optimized for.

The EFLX4K IO core replaces ~500 of the LUTs with about 1000 additional inputs and 1000 additional outputs.  The extra I/O are placed asymmetrically on one side since in our customers' typical application the input bus is much wider than the output bus.    This allows >1000 inputs and >1000 outputs to be routed to one side of even a single EFLX4K IO core (3.5K LUT4s in 1.0 square millimeters in TSMC16FFC/12FFC).  And the bus can run at 600-1000MHz in TSMC16FFC/12FFC depending on operating condition requirements.  

Two EFLX4K IO cores can bring in a 2000 bit bus on one side, 3 can do 3000 bits, etc.

EFLX4K IO cores are the exact same dimensions as EFLX4K Logic and DSP cores, so arrays of up to at least 7x7 can be constructed with a mix of EFLX4K IO, Logic and DSP cores.  

Click HERE for a Target Specification for the EFLX4K IO core.

The EFLX4K IO core can be ported to any CMOS process in ~6 months (less for processes where an EFLX4K Logic core is already designed: the IO version is a straightforward derivative).

Contact us at for more information.