"Gen 2" Architecture EFLX4K in Design for GF14LPP
Gen 2 architecture raises the bar on performance and density
The EFLX4K Logic and DSP cores in GF14LPP are in design now and will use our latest "Gen 2" architecture with the following improvements (ALL future EFLX implementations will also be "Gen 2"):
- Improved, higher performance XFLX™ interconnect, especially for larger arrays
- 6-input LUTs with Dual Outputs with 2 optional flip flops (can also be dual 5-input LUTs) - higher logic density and higher performance due to fewer LUT stages
- The Gen 2 combination of the improved interconnect and wider LUTs results in ~20-30% reduction in LUTs required and ~25% improvement in critical path performance compared to the first generation dual-4-input-LUTs in the same process node. A LUT6 has 1.6x the logic capacity of a single LUT4. Read here why 6-input LUTs give higher performance and higher density.
- In the EFLX4K DSP cores, the MACs are pipelined 10 in a row (compared to 5 in Gen 1) enabling higher performance for FIR/IIR filters, etc by using high speed data pipelining rather than using the general programmable interconnect network. HERE is a DSP Architecture brief with more details.
- DFT is enhanced to provide 99% coverage of all stuck-at faults with significantly higher coverage achieved with larger test vector sets, which Flex Logix provides.
- Test time for the Gen 2 architecture is enhanced with new parallel load logic which reduces test time by ~100x compared to the first generation
- Readback circuitry enables configuration bits to be read back and checked for soft errors (and corrected) as frequently as desired to improve reliability for High-Rel applications like automotive and defense/aerospace
GF14LPP is manufactured by GlobalFoundries in Malta, New York (outside of Albany) so it is of special interest for Aerospace applications which required US manufacturing.
A product brief for the GF14LPP implementation of the EFLX4K Logic and DSP cores is available HERE.
A validation chip will be manufactured, as is standard practice for us for every process port, and a detailed report will be available under NDA.
An evaluation board will also be made available for customers to directly test their RTL on real silicon.
Contact us at firstname.lastname@example.org for further information.