MAKE YOUR KEY RTL RECONFIGURABLE ANYTIME

We've all heard the phrase "RTL needs to be frozen by X Date".  

That's fine for some applications where things are 100% certain and stable.

But for many applications the requirements are unstable and continue to change:  for these applications consider reconfigurable RTL using EFLX embedded FPGA.  

Harvard approached Flex Logix in February 2017 asking to use EFLX in their new deep learning chip.  In deep learning, algorithms evolve quickly.  By the time a hard-wired chip appears in silicon, the algorithms are already out of date, so the pace of learning is slowed.  With embedded FPGA it is possible to implement some of the algorithms in reconfigurable logic so that algorithms can be updated and iterated in real time leading to a faster pace of innovation.  In less than 3 months Harvard was able to integrate a 10K LUT, 2x2 array of Gen2 EFLX-2.5K IP cores in TSMC16FFC (a mix of Logic and DSP) into their new deep learning chip which taped out in May 2017. Learn more about Harvard's Deep Learning Chip HERE.  In a future paper they will detail more about their architecture and findings.

Aerospace/Defense systems today account for >10% of all FPGA sales according to at least one market research report.  Embedded FPGA enables Aerospace/Defense systems to get the benefit of FPGA but at lower power, space, size and even with Rad-Hard or US fabrication options, if needed.  DARPA approached Flex Logix in 2016: they had determined that embedded FPGA was strategically critical for US Government Defense applications and that Flex Logix had the best solution.  DARPA licensed EFLX embedded FPGA for any US Government Performer in TSMC16FFC: the validation chip for a >100K LUT array is in fab along with the first design by a US Government Performer under the agreement.  Learn more about Aerospace/Defense applications HERE.

Networking chips are increasingly consumed by DataCenter companies who are increasingly requesting that all protocols (networking, security, storage) be programmable.  Today if a protocol standard changes, for a little while small volumes of traffic can be handled by much slower general purpose processors but as the volume of the new protocol increases, all of the switch chips in the Data Center need to be physically removed and replaced.  The DataCenters instead want to build the hardware and make changes in software and by reconfiguring programmable logic: this also enables them to develop protocols of their own for use within their own DataCenter ecosystem: they don't want to share this information with chip suppliers who are working with their competitors.  Learn more HERE.

Microcontroller chips today often have many dozens of mask variations where the only difference is which subset of Serial I/O protocols is implemented (SPI, I2C, UART, ...) and/or where the variation is which flavor of accelerator is implemented (encryption, decompression, etc).  As Microcontrollers are moving into 40nm where mask costs are close to $1M, multiple mask sets is an expensive proposition.  Instead the MCU can incorporate embedded FPGA for either flexible I/O and/or flexible accelerators so that multiple versions can be delivered from a single mask set.  Also, this then enables some processing of I/O to be moved into RTL from the processor for faster response and lower power.  Here are couple link: Flexible I/O and Battery Life Extension.

Even as something as simple as an I/O Pin Mux benefits from reconfigurability: HERE.

Learn more about EFLX embedded FPGA: start with our home page then explore our offerings for TSMC 40, 28 and 16nm.  We offer the most scalable, flexible solution across the most popular process nodes - and more are coming.

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