Software Reconfigurable I/O Pin Multiplexing

The following example shows how to use Flex Logix' reconfigurable RTL block to
1. implement I/O pin multiplexing so you can change the configuration any time,
2. get it right with less verification AND much more flexibility,
3. wire in additional signals "just in case" for extra visibility into internal operation,
4. you can even add logic to process internal signals (for example a counter).

The example below shows 16 GPIO, but with more EFLX-100, additional signals can be managed (and in different areas of the chip).

This example features the EFLX-100 reconfigurable RTL block: you can get more details on it under the products tab. It is available now in TSMC 40ULP and TSMC 16FF+/FFC; and soon in TSMC 28HPM/HPC/HPC+.  Check out our pages for each EFLX core by process node.

In SoCs, the I/O Pin Mux must be fixed at design time

The designer must choose which (large) set of SoC pins to bring out to a (limited) set of IO pins (e.g. GPIOs).
Due to different operation modes and debug modes, the IO mux can become a complex multiplexer.

And this complex IO Mux can be administratively difficult to track

  • often results in massive Excel sheets to capture every IO mode
  • must carefully control both data and direction
  • large, clumsy, hard-to-read, and easy to mis-wire (plus who really wants to do this task?)
  • any changes to IO configuration requires silicon re-spin

Then IO Mux in RTL is hard-coded
Any changes to IO configuration requires silicon re-spin.

and the above RTL is just for one output - repeat 16 times for all the GPIO.

IO Pin Mux in EFLX reconfigurable logic

Using EFLX, the IO Mux can be fully reconfigurable at any time

  • Just wire in all the I/O pins to EFLX
  • The smallest EFLX (EFLX-100) is 0.13mm2 in TSMC 40nm: 152 inputs & 152 outputs plus 120 look-up tables (LUTs) for combinatorial logics and 240 FFs
  • Re-configurable to ANY new IO configuration, in field, in < 1 ms


Now you only need to write RTL for the individual IO Mux mode that you want to configure at that time. (The EFLX Compiler translates your RTL into configuration bits which program the EFLX-100 Core to implement your RTL functionality).

Below is an example for one IO mode (OP_MODE[1])

In this example, some simple IO processing has been added: there is room for much more, intelligent IO processing if desired - and this can be reconfigured any time.

In this example, the resource usage of the one EFLX-100 core is

  • 144 out of 152 inputs (95%)
  • 96 out of 152 outputs (63%)
  • 6 out of 120 look-up-tables (5%): MUCH more processing could be added
  • IF you want a bigger IO mux, 2 cores can "tile" to provide much more IO and logic

Here is a PDF of an application note covering this content: click here.

Want to learn more?  Contact us at to
A) schedule a 1-hour technical overview in person or by web-ex (no NDA required) 
B) get a free evaluation license of EFLX Compiler in your target process to try out of some your RTL to check utilization and performance.