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EFLX™-2.5K IP Core

Our first product is SILICON PROVEN and available now, the EFLX-2.5K embedded FPGA core in TSMC® 28HPM/HPC/HPC+ process: 2,500 LUTs; 20Kbits RAM; interconnect network; boot/scan circuitry; multiple clocks; 632 inputs and 632 outputs. Density is 2.7K LUTs/sq mm. Just 6 layers of metal.

We call this a 2.5K LUT core: to be precise there are 2,520 dual 4-input LUTs in each EFLX-2.5K.  Each dual 4-input LUT has 2 bypassable flip flops on the outputs.  The total flip flop count per EFLX-2.5K is 6,304: 5040 on the outputs of the LUTs and 1,264 in the IO cells.

The core can be arrayed up to 7x7 for EFLX arrays of up to 122,500 LUTs.  We provide the GDS, LIB, LEF and Verilog files. 

The core has been validated in a 2x2 10K LUT test chip.  Worst case performance (125C, 0.81V, SS) for a 16-bit Counter is 507MHz (TSMC 28HPM: HPC/HPC+ performance is significantly faster). Measured performance for typical silicon: 600MHz for a complex, single stage RTL; 400MHz for a 13-tap, 2x8 multiplier FIR filter; and 370MHz for AES-128. Dynamic power: 40mW per 100MHz for a 100% utilized core with high activity factor (many RTL will be lower power). Static power 3mW/core.

See our product brief for the EFLX-2.5K IP core in TSMC 28HPM/HPC/HPC+.  Complete specifications and validation silicon report available under NDA.

EFLX-2.5K™ DSP IP Core

This core is optimized for signal processing intensive tasks.  Part of the general purpose logic portion the embedded FPGA core is replaced with 40 dedicated MACs  (shown below), each of which has a 22x22 multiplier with pre-adder and 48-bit post-adder/accumulator. It can also be configured for 11x11 complex multiply/add.  MACs can be concatenated for larger sizes.

FIR, IIR or CIC filters can be implemented consecutively in rows of DSP accelerator blocks without using LUTs or network interconnects.  Such filters, for example the 10-tap symmetric 22-bit FIR shown here, run 450 Megasamples/second (SS, Vj=0.81V, 125C) pipelined.  4 configurable operations may be switched cycle by cycle at run time.  See the DSP Applications page for more examples.

The EFLX-2.5K DSP FPGA core can be placed in arrays of up to 7x7 in any combination with EFLX-2.5K Logic FPGA cores.  The same software tools are used.

Complete specifications and validation silicon report available under NDA.