" Gen 1" EFLX®2.5K IP Core
Our first product is SILICON PROVEN and available now, the EFLX-2.5K embedded FPGA core in TSMC® 28HPM/HPC/HPC+ process: 2,500 LUTs; 20Kbits RAM; interconnect network; boot/scan circuitry; multiple clocks; 632 inputs and 632 outputs. Just 6 layers of metal. See our product brief for the EFLX-2.5K IP core in TSMC 28HPM/HPC/HPC+.
For new designs, we strongly recommend using the Gen 2 version below.
"Gen 2" EFLX4K embedded FPGA IP Core
Higher PERFORMANCE AND HIGHER DENSITY
VALIDATION CHIP NOW out of fab & in validation
An evaluation board will be available soon: inquire to firstname.lastname@example.org.
We have designed an enhanced EFLX4K IP core for TSMC 28HPC/HPC+ using our new "Gen 2" architecture with the following improvements listed below (already available for TSMC 16FFC/FFC+). The design IP is now available for licensing. A validation chip has been sent to fabrication (see bottom of the page).
Improved, higher performance interconnect, especially for larger arrays
6-input LUTs with Dual Outputs with 2 optional flip flops (can also be dual 5-input LUTs) - higher logic density and higher performance due to fewer LUT stages. Read here why 6-input LUTs provide higher density and higher performance.
The Gen 2 combination of the improved interconnect and wider LUTs results in ~20-30% reduction in LUTs required and ~25% improvement in critical path performance compared to the first generation dual-4-input LUTs in the same process node. A 6-input LUT is equivalent to 1.6 single-4-input LUTs for a 60% improvement in density.
In the EFLX4K DSP cores, the MACs are pipelined 10 in a row (compared to 5 in Gen 1) enabling higher performance for FIR/IIR filters, etc by using high speed data pipelining rather than using the general programmable interconnect network. HERE is a DSP Architecture brief with more details.
DFT is enhanced to provide 99% coverage of all stuck-at faults with significantly higher coverage achieved with larger test vector sets, which Flex Logix provides.
Test time for the Gen 2 architecture is enhanced with new parallel load logic which reduces test time by ~100x compared to the first generation
Readback circuitry (EFLX4K TSMC 16FFC/FF+ and all future implementations) enables configuration bits to be read back and checked for soft errors (and corrected) as frequently as desired to improve reliability for High-Rel applications like automotive and defense/aerospace.
Both all-Logic and DSP versions of the new "Gen 2" EFLX4K will be available.
The 28HPC/HPC+ EFLX4K uses just 6 metal layers (M1+5X) so is compatible with most 28HPC/HPC+ metal stacks.
Like all EFLX IP-cores, we use few layers of metal so we are compatible most metal stacks.
The EFLX4K cores, Logic and DSP, are interchangeable and can be arrayed up to at least 7x7 enabling ~50 different sizes addressing all customer needs.
TSMC28HPC+ performance is estimated to be ~0.7x TSMC16FFC performance. The estimate is based on SPICE simulations of the critical path of an core-crossing route: critical paths are typically long routes. You can use our EFLX Compiler for TSMC16FFC to get estimated performance.
If you are interested in detailed performance benchmarks or an area comparison with Menta for TSMC28HPM/C/C+, go to the web page HERE.
The EFLX cores operate over all voltage ranges supported by TSMC and over -40C to +125.
A validation chip is in fabrication to verify that silicon specs match predicted specs (see below): it is a 2x2 array with two EFLX4K DSP cores and two EFLX4K Logic cores plus RAM integrated between the tiles using RAMLinx. An evaluation board will be available to customers to test their RTL on actual silicon using this validation chip.