TIMING ANALYZER MODULE

Our new timing analyzer module allows you to see a histogram of all timing nets, then for each histogram bar to see the nets and then drill down into each net to see the stage by stage timing.  This level of timing information aids in determining how to optimize your RTL for improving critical path worst case performance.  Contact us for a demo and for a software evaluation license to try on your RTL: info@flex-logix.com

EFLX GUI - Timing Analyzer.png

 

DESIGN FLOW

Synplify: this widely used Synopsys tool takes your netlist/RTL and breaks it down into primitives in an EDIF format, which feeds into the EFLX Compiler.

EFLX™ Compiler:

  1. Input your RTL to see the resources required: # LUTs/Cores, DSP blocks and RAM.
  2. Configure your EFLX array: select the number and type of EFLX cores, the clocks, the I/O configuration connecting the array to the SoC, and the type and amount of Block RAM.
  3. Input your RTL with your configured array to determine the worst case path and frequency for your target process.
  4. Generate the bit file (bit stream) that programs the EFLX array in the SoC to execute your RTL.

The EFLX Compiler is now in use at customers for designs and evaluation.

We can demonstrate our tools by Web-ex and run RTL for a customer, if they wish..  

Here is a video demonstration of the key steps in compiling an RTL design for EFLX embedded FPGA to determine performance and LUT count.  (the timing files vary by process node).

For qualified customers we can provide free evaluation licenses.  Contact us at info@flex-logix.com.

[Synopsys is a Registered Trademark of Synposys, Inc.]