NEW "Gen 2" Architecture

The EFLX-100 and EFLX-2.5K in TSMC 16FF+/FFC use our latest "Gen 2" architecture with the following improvements (ALL future EFLX implementations will also be "Gen 2"):

  • Higher performance interconnect, especially for larger arrays
  • 6-input LUTs with Dual Outputs with 2 optional flip flops (can also be dual 5-input LUTs) - higher logic density and higher performance due to fewer LUT stages
  • DFT enhancements for faster test and increased reliability, which will be detailed in Q2

EFLX-100 for TSMC® 16FF+/FFC is available now

EFLX-100 in TSMC 16FF+/FFC enables programmable networking chips with wide, reconfigurable logic from 100 to 2500 LUTs running ~1GHz (exact speed depends on the RTL and the voltage range).  

The EFLX-100 core in TSMC 16FF+/FFC has been enhanced to provide higher performance for the wide logic cones of network control logic:

  • 96 each of 6-input LUTs (also useable as dual 5-input LUTs): wider LUTs mean wide logic cones can be handled in fewer stages meaning higher performance and higher density
  • 224 inputs and 224 output: more inputs means wider logic paths can be handled in fewer EFLX-100 cores

All voltage ranges are supported for 16FF+ and 16FFC over the full -40 to 125C temperature range.

A single EFLX-100 core is 0.05 mm2 in size. 

The EFLX-100 core tiles in ~25 array sizes from 100 to 2,500 LUTs.

TRY OUT YOUR RTL: get a software evaluation license for the EFLX Compiler with worst-case timing files for EFLX-100 in TSMC 16FF+/FFC to see how your RTL performs and how many LUTs it uses.  Email info@flex-logix.com to arrange your license. 

Here is the TSMC 16FF+/FFC EFLX-100 core product brief.

A much more detailed data sheet is available under NDA: contact us at info@flex-logix.com.

A validation chip will tape-out early January to enable full validation in silicon in early 2017 of full performance over worst case conditions.  The validation chip includes two array sizes and checks out the circuitry for "tiling" into larger arrays.  An on-chip PLL enables generating clocks >1GHz.  On-chip SRAM provides a "tester on a chip" to enable >1GHz operation at worst case conditions to verify performance versus simulation.  On-chip Process/Voltage/Temperature monitors ensure testing is being done at worst case conditions on-die.

 

EFLX-2.5K Logic/DSP for TSMC 16FF+/FFC is in design

Availability of the EFLX-2.5K Logic and DSP IP cores for TSMC 16FF+/FFC are expected in early 2017.

Here is a preliminary product brief for EFLX-2.5K for TSMC 16FFC/FF+.

The EFLX-2.5K cores in TSMC 16FF+/FFC will utilize the large 6-input LUTs from the EFLX-100 core in TSMC 16FF+/FFC.

Both will be validated in silicon once design is complete.