EFLX®100 for TSMC® 40ULP/LP is Available Now
The EFLX100 takes only 0.13mm2 in TSMC ULP/LP and is available in multiple versions with varying VT masks and voltages to give you the performance/power tradeoff you want for your application. It can be used stand-alone (1x1 array) or in up to a 5x5 array.
The EFLX100 uses 5 metal layers (M1+4) so it is compatible with almost all 40ULP metal stacks.
The GDS is compatible with TSMC 40LP as well, though timing is different.
The LUT in the EFLX100 in TSMC40 is a dual 4-input LUT with two bypassable flip flops on the outputs. We call it the EFLX100 because it is about 100 LUTs, but there are actually 120 dual 4-input LUTs in the logic-only EFLX100. The flip flop count is 544 per EFLX100: 240 flip flops on the LUT outputs and 304 flip flops in the EFLX100 IO cells (152 inputs and 152 outputs).
Applications include: software reconfigurable I/O Mux; software reconfigurable I/O crossbar for GPIO; reconfigurable RTL block on your bus to program for varying customer applications; reconfigurable DSP accelerator for varying customer applications; control logic; etc.
Click TSMC40ULP/LP EFLX100 Product Brief for detailed specifications.
A validation chip has been fully tested over temperature and voltage to prove out all 10 combinations of the EFLX100 IP core. Ask for a validation report.
Here is a brief demo showing our test setup at 50MHz (actual operating frequency is often higher depending on the VT options chosen and the RTL being run).
Each array has both Logic and DSP versions of the EFLX100 IP core. We do arrays of at least 2x2 to prove-out the top level interconnect that is used to array the IP cores into larger arrays. We have 5 VT combinations that customers are interested in: customers typically have already chosen the VT masks they are going to use and we must be compatible with their choice. We can utilize two VT masks if the customer has them: for example in eHVT/SVT, the configuration bit cells and other "static logic" use eHVT for minimum power while the SVT mask is used for the switching logic in the critical path of performance. We have power domains dedicated to each EFLX array and separately for SRAM, I/O and PLL so we can measure voltage, power, performance precisely for each array. We have SRAM on the chip so we can load data patterns into an SRAM then run the patterns at full speed on chip with results going into a second SRAM. A PLL gives precise timing control. A VDD monitor tells us the on chip voltage. And a VCO gives process data. When validated (in process now) results will be available under NDA.
The EFLX Compiler with TSMC 40LP/ULP timing files is available now. Contact us at info@flex-logix for an evaluation license to check out your RTL's area and performance.
More details available under NDA - contact us at info@flex-logix.