A New Concept: Virtual Array Architecture for eFPGA
Until now FPGAs have been programmed as one big block. Today things change.
eFPGA is enabling new compute architectures and that is causing our customers to ask us to solve new problems and enable new ways of using eFPGA.
Flex Logix' unique tiling architecture makes it easy for us to enable modular FPGA computing. The first step is Virtual Arrays which give customers and IP suppliers several benefits: bit streams can be distributed rather than RTL but can interface to adjacent unprogrammed eFPGA tiles; placement, power and timing can be determined in advance and "locked" because the bit stream is not changed; avoid re-running P&R on the entire array when the virtual array does not change.
Virtual Array Architecture enables you to design an SoC where you program part of the embedded FPGA and leave the rest for your customer to program: but your design is masked from theirs.
Or a Virtual Array can be used by an IP supplier to distributed their IP, such as encryption algorithms, to customers.
Recently at D&R IP-SOC Conference in Silicon Valley, Cheng Wang, Senior VP Engineering and Co-Founder of Flex Logix, presented a paper on Flex Logix' new Virtual Array Architecture for eFPGA: SEE THE SLIDES HERE.
The EFLX Compiler recent release now supports Virtual Array Architecture: you can try it on your RTL design and also on our EFLX200 Evaluation Board. Contact us at firstname.lastname@example.org for further information.