Tell them Flex Logix needs another Hardware Design Manager to implement EFLX eFPGA in leading edge process nodes.  See our CAREERS PAGE then contact


arraylinx™ enables dozens of array sizes in days using a silicon-proven building block

A critical need for customers is to have both silicon proven IP AND a wide range of array sizes.  When we started Flex Logix,  Co-Founder Cheng Wang realized this was a difficult problem.  His solution was to design an eFPGA core which is a complete eFPGA, but which when arrayed together by abutment creates larger arrays of dozens of sizes:  this is achieve by having a top level of interconnect, ArrayLinx™, which hooks up when the cores are abutted.  The details of this is covered in a new US Patent issued 27 February 2018, US Patent 9,906,225.  See the press release for more details.  Each of our validation chips for every process port has at a minimum a 2x2 array so we validate the top level interconnect as well as the eFPGA IP core itself.  Because of this key invention, we can deliver you multiple different array sizes and configurations for your design - and if you change your mind, we can deliver a larger or smaller array in days: just the time it takes to re-compute the timing files for the new array size/configuration.

Want more details? Go to our page that explains tiling in more detail HERE.

Interview with CEO of Flex Logix "The Race to Accelerate"

female speed skaters.jpg



The HiPer Consortium, made up of Israeli semiconductor and systems companies, including Mellanox, Satixfy, DSP Group and AutoTalks, will use Flex Logix® EFLX eFPGA in a 16nm architecture and technology evaluation chip under a license with Bar Ilan's SoC Lab which is also part of the HiPer Consortium.  Bar Ilan is one of the top technology universities in Israel.

"After evaluating multiple suppliers of embedded FPGA IP, we chose the Flex Logix EFLX platform because it provided the best technical solution and offered the most scalability for a wide range of applications," said Aner Shoam, CTO of HiPer Consortium.  "We are excited by the flexibility enabled by EFLX, which will allow us to customize a single chip for multiple markets and/or upgrade the chip while in the system to adjust to changing standards such as networking protocols."

See the press release HERE.

Here are some other customers we can talk about publicly...


SiFive has selected EFLX eFPGA for it's customizable, open-sourced-enabled semiconductors for its Freedom Platform Chips through the DesignShare program which eases time to market and removes traditional barriers to entry that have blocked smaller companies from developing custom silicon.  SiFive's Platform Chips are based on the RISC-V architecture.  SiFive's Freedom U500 Platform chips for customizable SoCs are 28nm and the Freedom U300 Platform for customizable MCUs are 180nm.  Flex Logix will provide several sizes of EFLX eFPGA arrays for each platform.  Flex Logix and SiFive engineering teams are working together first to integrate eFPGA into a tape-out of the SiFive U500 base platform for customer evaluation using SiFive evaluation boards and software: more details to follow.  Flex Logix will provide EFLX eFPGA for 180nm on demand for the U300 base platform.  In both cases, EFLX eFPGA will connect directly to the processor bus and to up to 64 GPIO, enabling implementation of customer-specific reconfigurable accelerators (see Accelerators for information on how eFPGA provides speed-up of 30-100x) and customer-specific I/O subsystems, including programmable Serial I/O (see Flexible I/O).  See the SiFive page for more details.  Click HERE for the press release. 

sandia national laboratories logo.png

Sandia National Laboratories has licensed Flex Logix' Gen 2 EFLX4K logic core which Flex Logix has ported to Sandia's proprietary 180nm process.  All IP deliverables have been made.  Sandia will use EFLX flexible logic in development of multiple Sandia chip products for use in Sandia projects.  See the press release HERE.  The Gen 2 EFLX4K core in Sandia's 180nm process is the same digital architecture as in TSMC 16FF+/FFC and TSMC 28HPC/HPC+ and is programmed using the same EFLX Compiler.  Sandia will present a paper at GOMACTech Conference in March describing their Rad-Hard 180nm EFLX4K eFPGA core and its application for System-on-Chip.


Harvard approached us in February 2017 asking to use EFLX in their new TSMC16FFC deep learning chip.  In deep learning, algorithms evolve quickly.  By the time a hard-wired chip appears in silicon, the algorithms are already out of date, so the pace of learning is slowed.  With embedded FPGA some of the algorithms can be implemented in reconfigurable logic so they can be iterated in real time.  In less than 3 months Harvard was able to integrate a 16K LUT, 2x2 array of Gen2 EFLX4K IP cores in TSMC16FFC (a mix of Logic and DSP) into their chip and taped out in May 2017.   Harvard will publish their results at a future conference.  The Harvard press release can be found HERE.

DARPA cropped transparent.jpg

DARPA, the US government's Defense Advanced Research Projects Agency, has selected EFLX embedded FPGA and entered into an agreement for it to be made available to any company or government agency designing chips in TSMC® 16FFC for use by any branch of the US Government.  Flex Logix has agreements with other organizations and companies, but DARPA is the first to be made public.  Flex Logix EFLX4K IP Cores in TSMC16FFC are available now.  The DARPA press release can be found HERE.


2017 09 TSMC Partner of the Year 2017 -- New IP.JPG


Six Game Changer Companies to Watch in 2018: click HERE.
TSMC OIP Partner of the Year 2017: press release HERE.
Flex Logix joins TSMC IP Alliance: press release HERE.
EE Times Top 60 to Watch : SEE HERE.

Follow us on Twitter @efpga or Linked-in for the latest news on Flex Logix.



Three FPGA Interconnect Patents Awarded to Cheng Wang

XLFX™ enables dense, portable, scalable eFPGA

2014 Boundary-Less Radix Interconnect  Network.png

XFLX™, the innovative interconnect network technology in EFLX eFPGA is now protected by three patents awarded to Cheng Wang, Co-Founder of Flex Logix® (one of which is joint with Dejan Markovic, another Co-Founder).  See Flex Logix Co-Founder Cheng Wang Awarded Three FPGA Interconnect Patents.  This innovative technology was first described in a 2014 ISSCC Paper which won the ISSCC Outstanding Paper Award; further improvements have been made since Flex Logix was started.  In a traditional FPGA fabric, ~80% of the area is programmable interconnect and only ~20% is programmable logic.  This new interconnect is almost twice as dense and is implemented in fewer metal layers: critical advantages for embedded FPGA.

Customers want eFPGA IP that is Silicon Proven, Dense and that they can use on their process node/variation and metal stack and in the array size they want without changing the GDS that was proven in Silicon.  Flex Logix can do this because of our patented XFLX interconnect.

Click HERE to read on   See our new white paper: HERE.   And read a summary HERE.

Reconfigure your RTL in chip and in system whenever you want

Make one chip look like dozens: save the time and costs of multiple mask sets.
Allow your chip to be able to upgrade to handle new standards and specs: your chip will have a longer life and be more valuable.
We provide embedded FPGA to make this possible: any process, any size, optional DSP/RAM and programming software.

Flexible, Proven Building Blocks: We Deliver More, Sooner 

Our management team has the experience to grow Flex Logix rapidly while meeting commitments.  Our engineers have worked at many of the world's best chip companies on processes from 180nm to 7nm designing high volume ICs.  We can meet your needs and we will meet our commitments.  

We prove our Hard IP in Silicon before you use it.  We execute effectively and quickly: in 2.5 years we have designed EFLX™ in TSMC 40, 28 and 16FF.  Our lead customers have their chips working with EFLX arrays embedded.

EFLX150 1x1 to 5x5.jpg

We will port to TSMC 7/22/55/65/90/180nm on demand.  We can port to any CMOS process, foundry or captive, in ~6 months from receipt of PDK and standard cell library -- we only port with a committed customer to ensure we have a partner to help us optimize our digital architecture for the target process.  For example, in 40ULP we optimized for numerous power management modes with rapid transitions, 0.5V state retention and even 0.5V operation if needed.  Whereas in 16FF customers want performance, performance, performance.  See EFLX Implementation Options for a full list. In all nodes it is the same digital architecture with the same programming software.

EFLX4K 1x1 to 7x7.jpg

In each process node we implement up to 4 IP cores: EFLX150 and EFLX4K; each has an all-logic version and a version with embedded Multiplier-Accumulators for DSP Acceleration.  Each IP core is a stand-alone FPGA, but incorporates additional top-level interconnect which allows automatic connection to adjacent IP cores turning them automatically into larger EFLX arrays.

Our innovative building block approach means we can deliver any size embedded FPGA from 100 LUTs to 200K LUT4s, with about 75 sizes in between: and each size can be further customized with the mix of DSP acceleration and/or RAM that you might also need.  We have even fabricated an EFLX200K array which is in characterization now.

IF 200K LUTs is too small for you, inquire about our roadmap to ~800K LUT4 arrays which we can implement quickly:

Gen 2 EFLX Architecture Available now for TSMC 16nm and soon 28nm

The new EFLX-2.5K cores (Logic and DSP) available in TSMC 16FFC/FF+/12FFC feature the new Gen 2 Architecture with the following improvements:

  • 6-input LUTs and an improved interconnect that result in ~30% fewer LUTs and ~25% faster critical path performance compared to our "1st Gen" architecture
  • MACs pipelined 10 in a row (versus 5 in "1st Gen") for higher performance for FIR/IIR filters and other DSP functions without needing to use the general interconnect network
  • DFT enhancements to ensure >98% coverage of all stuck-at faults with much higher coverage possible with larger vector sets, provided by Flex Logix
  • A parallel test configuration load mode that results in ~100x faster test times for Gen 2 
  • Readback circuitry to check, and correct, configuration bits for soft errors as frequently as desired for High-Reliability applications like Automotive and Aerospace/Defense

See our TSMC16FFC/FF+/12FFC EFLX-2.5K/EFLX-100 web page for more details.  A validation chip is in fab now that has a maximum size 7x7 array of EFLX-2.5K DSP and Logic cores with >>100K LUTs and >500 MACs: high level GDS is shown to the right.

Our TSMC 28HPC/HPC+ core is being redesigned to incorporate all Gen 2 features: see the web page here.

EFLX® Compiler - try it yourself!

Our software, the EFLX Compiler,  converts your RTL into a bit stream which you load into the EFLX FPGA array to program it to run your RTL including DSP and Block RAM.  The EFLX Compiler is in use at our lead customers and is now available for evaluation for qualified customers: contact us at

The first module of our GUI is now available: Timing Analyzer.  More modules will be released in Q4.

Learn more about EFLX Compiler here.

Need a summary to circulate to the team?

Download our 4-page PDF overview of our technology and company:  click here to get the PDF.
Download our 2-page product brief on the EFLX100 logic/DSP cores for TSMC 40ULP/LP: click here to get the PDF.
Download our 2-page product brief on the EFLX4K logic/DSP cores for TSMC 28HPC/HPC+: click here to get the PDF.
Download our 2-page product brief on the EFLX150 logic core for TSMC 16FF+/FFC/12FFC: click here to get the PDF
Download our 2-page product brief on the EFLX4K logic/DSP cores for TSMC 16FF+/FFC/12FFC: click here to get the PDF.
Download our 2-page target spec on the EFLX4K logic/DSP cores for GF 14LPP:  click here to get the PDF.

Copyright © 2015-2018 Flex Logix Technologies, Inc. EFLX and Flex Logix are Trademarks of Flex Logix Technologies, Inc.