NEW NAMING CONVENTION FOR NEW GEN 2 EFLX
Our Gen 2 EFLX IP cores use 6-input-LUTs, as do the latest Xilinx FPGAs. But Xilinx names their products based on the capacity in LUT4 equivalents (one 6-input-LUT = 1.6 4-input-LUTs). We are now adopting this naming convention since it is one customers are familiar with. So for Gen 2, our EFLX IP cores are now the EFLX 150 and EFLX4K going forward. Our product briefs and data sheets will clearly indicate the number of LUT6s as well. Click HERE for why we shifted to 6-input-LUTs for higher speed and density.
SANDIA LABS SELECTS EFLX® FOR MULTIPLE CHIP PRODUCTS
Sandia National Laboratories has licensed Flex Logix' Gen 2 EFLX4K logic core which Flex Logix has ported to Sandia's proprietary 180nm process. All IP deliverables have been made. Sandia will use EFLX flexible logic in development of multiple Sandia chip products for use in Sandia projects.
See the press release HERE.
The Gen 2 EFLX4K core in Sandia's 180nm process is the same digital architecture as in TSMC 16FF+/FFC and TSMC 28HPC/HPC+ and is programmed using the same EFLX Compiler.
If you want flexibility for chips you design for your own fab, look here for details on options for custom process ports of EFLX. We can port to your proprietary process typically in ~6 months.
FLEX LOGIX™ WINS 2017 TSMC OIP PARTNER OF THE YEAR AWARD FOR NEW IP
At the TSMC Open Innovation Platform Conference in Santa Clara, California, TSMC's Cliff Hou, Vice President of R&D/Design and Technology Platform, awarded Flex Logix with the 2017 TSMC Open Innovation Platform Partner of the Year Award for New IP.
Flex Logix is very proud to win this award! We have worked with TSMC for just 3 years, but we have our IP available on TSMC 16/28/40 and are the first embedded FPGA Supplier to join the TSMC IP Alliance. We look forward to a long relationship with TSMC providing the most scalable, flexible embedded FPGA solution across the full range of TSMC process nodes.
FLEX LOGIX JOINS TSMC IP ALLIANCE PROGRAM
Flex Logix has worked with TSMC since it's founding in 2014. In just three years we have developed and validated our embedded FPGA technology on TSMC 16nm, 28nm and 40nm. We have met TSMC's standards for design methodology, rigorous engineering checks and sign-offs, documentation, and engineering validation. We offer the widest range of embedded FPGA array sizes from 100 to 200K LUT4s and with the most options for DSP and any type/size of embedded RAM. And we expect, as customers need, we will make our EFLX embedded FPGA available on every TSMC node from 7nm to 180nm.
We are proud to be chosen by TSMC to be the first embedded FPGA supplier in the TSMC IP Alliance and will continue to maintain high engineering standards in supporting our mutual customers. We appreciate TSMC's support and vote of confidence.
If you have not talked with us yet, or want an update, please contact us at email@example.com to set up an engineering update.
ON-CHIP DEBUGGER/LOGIC ANALYZER
Check out our latest application note showing how to improve your chip management functionality HERE.
See FLEX LOGIX™ in october at arm techcon
& in November at TSMC OIP Shenzhen, gsa asia executive forum tapei, iccad beijing and semisrael tel aviv
See our events page for a detailed list of all events.
Follow us on Twitter @efpga or Linked-in for the latest news on Flex Logix.
See our Software station for demos of our flow and our newest module for Timing Analysis; the full GUI interface will be rolled out over the next few months.
Reconfigure your RTL in chip and in system whenever you want
Make one chip look like dozens: save the time and costs of multiple mask sets.
Allow your chip to be able to upgrade to handle new standards and specs: your chip will have a longer life and be more valuable.
We provide embedded FPGA to make this possible: any process, any size, optional DSP/RAM and programming software.
Check our applications pages for applications for detailed app notes for I/O Muxing, Reconfigurable I/O, Battery Life Extension, Reconfigurable Accelerators and more. Embedded FPGA is being used and/or evaluated for Aerospace/Defense, MCU, Networking, Data Center, Wireless Base Stations and more.
Leaders Select Embedded FPGA
We are working with many companies and organizations, but only a few will let us talk publicly about them.
Harvard approached us in February 2017 asking to use EFLX in their new TSMC16FFC deep learning chip. In deep learning, algorithms evolve quickly. By the time a hard-wired chip appears in silicon, the algorithms are already out of date, so the pace of learning is slowed. With embedded FPGA some of the algorithms can be implemented in reconfigurable logic so they can be iterated in real time. In less than 3 months Harvard was able to integrate a 16K LUT, 2x2 array of Gen2 EFLX4K IP cores in TSMC16FFC (a mix of Logic and DSP) into their chip and taped out in May 2017. Harvard will publish their results at a future conference. The Harvard press release can be found HERE.
DARPA, the US government's Defense Advanced Research Projects Agency, has selected EFLX embedded FPGA and entered into an agreement for it to be made available to any company or government agency designing chips in TSMC® 16FFC for use by any branch of the US Government. Flex Logix has agreements with other organizations and companies, but DARPA is the first to be made public. Flex Logix EFLX4K IP Cores in TSMC16FFC are available now. The DARPA press release can be found HERE.
Flexible, Proven Building Blocks: We Deliver More, Sooner
Our management team has the experience to grow Flex Logix rapidly while meeting commitments. Our engineers have worked at many of the world's best chip companies on processes from 180nm to 7nm designing high volume ICs. We can meet your needs and we will meet our commitments.
We prove our Hard IP in Silicon before you use it. We execute effectively and quickly: in 2.5 years we have designed EFLX™ in TSMC 40, 28 and 16FF. Our lead customers have their chips working with EFLX arrays embedded.
We will port to TSMC 22/55/65/90/180nm on demand. We can port to any CMOS process, foundry or captive, in ~6 months from receipt of PDK and standard cell library -- we only port with a committed customer to ensure we have a partner to help us optimize our digital architecture for the target process. For example, in 40ULP we optimized for numerous power management modes with rapid transitions, 0.5V state retention and even 0.5V operation if needed. Whereas in 16FF customers want performance, performance, performance. See EFLX Implementation Options for a full list. In all nodes it is the same digital architecture with the same programming software.
In each process node we implement up to 4 IP cores: EFLX150 and EFLX4K; each has an all-logic version and a version with embedded Multiplier-Accumulators for DSP Acceleration. Each IP core is a stand-alone FPGA, but incorporates additional top-level interconnect which allows automatic connection to adjacent IP cores turning them automatically into larger EFLX arrays.
Our innovative building block approach means we can deliver any size embedded FPGA from 100 LUTs to 200K LUT4s, with about 75 sizes in between: and each size can be further customized with the mix of DSP acceleration and/or RAM that you might also need. We have even fabricated an EFLX200K array which is in characterization now.
IF 200K LUTs is too small for you, inquire about our roadmap to ~800K LUT4 arrays which we can implement quickly: firstname.lastname@example.org.
Gen 2 EFLX Architecture Available now for TSMC 16nm and soon 28nm
The new EFLX-2.5K cores (Logic and DSP) available in TSMC 16FFC/FF+/12FFC feature the new Gen 2 Architecture with the following improvements:
- 6-input LUTs and an improved interconnect that result in ~30% fewer LUTs and ~25% faster critical path performance compared to our "1st Gen" architecture
- MACs pipelined 10 in a row (versus 5 in "1st Gen") for higher performance for FIR/IIR filters and other DSP functions without needing to use the general interconnect network
- DFT enhancements to ensure >98% coverage of all stuck-at faults with much higher coverage possible with larger vector sets, provided by Flex Logix
- A parallel test configuration load mode that results in ~100x faster test times for Gen 2
- Readback circuitry to check, and correct, configuration bits for soft errors as frequently as desired for High-Reliability applications like Automotive and Aerospace/Defense
See our TSMC16FFC/FF+/12FFC EFLX-2.5K/EFLX-100 web page for more details. A validation chip is in fab now that has a maximum size 7x7 array of EFLX-2.5K DSP and Logic cores with >>100K LUTs and >500 MACs: high level GDS is shown to the right.
Our TSMC 28HPC/HPC+ core is being redesigned to incorporate all Gen 2 features: see the web page here.
EFLX™ Compiler - try it yourself!
Our software, the EFLX Compiler, converts your RTL into a bit stream which you load into the EFLX FPGA array to program it to run your RTL including DSP and Block RAM. The EFLX Compiler is in use at our lead customers and is now available for evaluation for qualified customers: contact us at email@example.com.
The first module of our GUI is now available: Timing Analyzer. More modules will be released in Q4.
Need a summary to circulate to the team?
Download our 4-page PDF overview of our technology and company: click here to get the PDF.
Download our 2-page product brief on the EFLX100 logic/DSP cores for TSMC 40ULP/LP: click here to get the PDF.
Download our 2-page product brief on the EFLX4K logic/DSP cores for TSMC 28HPC/HPC+: click here to get the PDF.
Download our 2-page product brief on the EFLX150 logic core for TSMC 16FF+/FFC/12FFC: click here to get the PDF
Download our 2-page product brief on the EFLX4K logic/DSP cores for TSMC 16FF+/FFC/12FFC: click here to get the PDF.
Copyright © 2015-2017 Flex Logix Technologies, Inc. EFLX and Flex Logix are Trademarks of Flex Logix Technologies, Inc.