DARPA SELECTS EFLX
DARPA, the US government's Defense Advanced Research Projects Agency, has selected EFLX embedded FPGA and entered into an agreement for it to be made available to any company or government agency designing chips in TSMC® 16FFC for use by any branch of the US Government. Flex Logix has agreements with other organizations and companies, but DARPA is the first to be made public. Flex Logix is in design of the EFLX-2.5K in TSMC16FFC now: it will be available in Q2 for use by the US Government and by any company for commercial market applications in Networking, Wireless Base Stations, Data Centers and others. See our News & Events page for more details in the press release and press coverage. Flex Logix will be presenting more details on the EFLX-2.5K in TSMC16FFC at the upcoming Government Microcircuits Technology Conference in Reno NV, March 21+22. Commercial customers can learn more about EFLX in TSMC 16FF+ and 16FFC at the upcoming TSMC Technology Symposiums in Santa Clara, Austin and Boston.
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EFLX AVAILABLE NOW FOR TSMC16FF+ & TSMC 16FFC
This is our 2nd generation architecture: all future EFLX arrays will also incorporate these features
- 6-input LUTs: more logic capacity and higher performance by reducing LUT stages needed for complex logic cones
- Faster interconnect, especially for larger arrays
- DFT enhancements: these will be detailed in an announcement in Q2
EFLX-100 enables programmable control logic for networking chips with 100-2500 LUTs of reconfigurable logic running at line rates.
The EFLX-100 embedded FPGA IP core has completed design and is now available for both TSMC16FF+ and TSMC 16FFC. Performance for wide, single-stage logic is expected to be ~1GHx at worst case PVT conditions: of course this will depend on the exact RTL and the voltage range selected. A validation chip is in fabrication and validation in silicon is expected in early 2017. A product brief and more details are available on our T16FF+/16FFC page.
The EFLX-2.5K Logic and DSP embedded FPGA IP cores are now in design for TSMC 16FF+ and 16FFC: they will be available early in 2017. A preliminary product brief is available on our T16FF+/16FFC page.
Flex Logix now has IP available on TSMC 40, 28 and 16: 3 IP ports in total in about 2.5 years. This is possible because of an architecture designed for density, scalability and portability. And we are staffing up more to meet growing customer demand.
Embedded FPGA for Architects & Physical Designers
Here is a link to the PDF of our keynote talk at REUSE2016: Embedded FPGA for Architects & Physical Designers.
Flexible, Proven Building Blocks: We Deliver More, Sooner
Our management team has the experience to grow Flex Logix rapidly while meeting commitments. Our engineers have worked at many of the world's best chip companies on processes from 180nm to 7nm designing high volume ICs. We can meet your needs and we will meet our commitments.
We prove our Hard IP in Silicon before you use it. We execute effectively and quickly: in 2.5 years we have designed EFLX™ in TSMC 40, 28 and 16FF. Our lead customers have their chips working with EFLX arrays embedded.
We will port to TSMC 12/22/55/65/90/180nm on demand. We can port to any CMOS process, foundry or captive, in ~6 months from receipt of PDK and standard cell library -- we only port with a committed customer to ensure we have a partner to help us optimize our digital architecture for the target process. For example, in 40ULP we optimized for numerous power management modes with rapid transitions, 0.5V state retention and even 0.5V operation if needed. Whereas in 16FF customers want performance, performance, performance. See EFLX Implementation Options for a full list. In all nodes it is the same digital architecture with the same programming software.
In each process node we implement up to 4 IP cores: EFLX-100 and EFLX-2.5K; each has an all-logic version and a version with embedded Multiplier-Accumulators for DSP Acceleration. Each IP core is a stand-alone FPGA, but incorporates additional top-level interconnect which allows automatic connection to adjacent IP cores turning them automatically into larger EFLX arrays.
Our innovative building block approach means we can deliver any size embedded FPGA from 100 LUTs to 100K LUTs, with about 75 sizes in between: and each size can be further customized with the mix of DSP acceleration and/or RAM that you might also need.
Our first two EFLX arrays have dual-4-input LUTs.
Our new "Gen 2" architecture, starting with TSMC 16, has 6-input LUTs with dual outputs/flip-flops; faster interconnect; and new DFT features which will be described in detail shortly.
Join our other customers who are designing with EFLX embedded FPGA. Check out our Experience page.
Reconfigure your RTL in chip and in system whenever you want
Make one chip look like dozens: save the time and costs of multiple mask sets.
Allow your chip to be able to upgrade to handle new standards and specs: your chip will have a longer life and be more valuable.
We provide embedded FPGA to make this possible: any process, any size, optional DSP/RAM and programming software.
(Re)Configurable Clouds will change the world
Doug Burger, Microsoft talks about how the ability to reprogram a datacenter's hardware protocols (networking, storage, security) is a game changer: click here for his presentation at FPL2016.
EFLX™ embedded FPGAs give you the capability to implement reconfigurability in your Networking & Communications SoCs. We have EFLX available now in TSMC28HPM/HPC and very soon in TSMC16FF for your new designs.
Easy & More Powerful I/O Pin-Muxing
Most chips have pin mux-es. They are important but tedious and prone to human error. EFLX™ makes it easy AND fast to wire many more signals into the pin mux for great observability. The I/O Pin Mux can be reprogrammed at any time! Check out our IO Multiplexing page.
Extended Battery Life for IoT and Microcontrollers
Many times we hear "but FPGAs are high power" - maybe the chips are, but embedded FPGA can be very energy efficient. Tony Kozaczuk, our new Director of Solutions Architecture, has done an analysis showing that for the DSP functions he analyzed, a small EFLX array can take 2-5x less energy than an embedded processor (and that's before considering the energy for the ARM memory accesses), and executes faster as well. So an EFLX array can be used to do the repetitive DSP functions in a battery-backed chip, only waking up the processor for more complex tasks. See Tony's analysis on this page, with a link to the slide deck: set up a call with Tony to discuss your application: email email@example.com.
Flexible, Reconfigurable I/O for Microcontrollers & IoT
Tony Kozaczuk, Director of Solutions Architecture, joined us mid-2016 from Intel where he was Lead Systems Architect for multiple CPUs and before that an architect at Sun. He has now produced his 2nd application note showing how to connect EFLX™ to the APB bus and implement GPIO ports and serial interfaces in reconfigurable RTL, enabling one 40nm mask set to support dozens of different customers requested variations in GPIO/serial interfaces (and quickly). Check out the app note on this page: Flexible I/O.
UART, SPI & I2C Serial Interface IP Cores for EFLX
Most chip companies have their own RTL for the functions they want to program in embedded FPGA, but some have requested the availability of proven commercial IP from leading suppliers, especially for Serial Interface IP. Flex Logix has worked with CAST and SoC Solutions to qualify their UARTs, SPI and I2C Serial Interface Cores. The application note available on our Flexible I/O Page gives details of the LUT count and performance in TSMC® 40ULP for these IP cores.
EFLX™ for TSMC 40ULP in Validation
EFLX-100 Logic and DSP cores in multiple VT combinations are available now for integration in MCU, IOT and other ICs.
A validation chip will prove out all 10 versions of the EFLX-100 core: the validation chip is back, is fully functional and is being tested for performance over voltage ranges for the 10 versions and at temperature extremes. See our TSMC 40ULP page for information on the validation chip.
EFLX™ for TSMC 28HPM/HPC/HPC+ Proven in Silicon
TSMC 28 page here. Ask to see our validation report, under NDA.
EFLX™ Compiler - try it yourself!
Our software, the EFLX Compiler, converts your RTL into a bit stream which you load into the EFLX FPGA array to program it to run your RTL including DSP and Block RAM. The EFLX Compiler is in use at our lead customers and is now available for evaluation for qualified customers: contact us at firstname.lastname@example.org.
Need a summary to circulate to the team?
Download our 4-page PDF overview of our technology and company: click here to get the PDF.
Download our 2-page product brief on the EFLX-100 logic/DSP core for TSMC 40ULP/LP: click here to get the PDF.
Download our 2-page product brief on the EFLX-2.5K logic/DSP core for TSMC 28HPM/HPC/HPC+: click here to get the PDF.
Download our 2-page product brief on the EFLX-100 logic core for TSMC 16FF+/FFC: click here to get the PDF.
Download our DSP Technology Overview which explains the DSP core features for EFLX-100 and EFLX-2.5K: click here for PDF.
Help us make the world a more flexible place!
We are hiring: engineering, applications, sales. See our careers page. We want great people who want to make a difference.
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