EFLX FPGA AVAILABLE FOR CHIPLETS
Customers at times may prefer to integrate FPGA by using multi-chip packaging: this will require a bumped FPGA die with signaling optimized for the customers' specs. Flex Logix already has such a die in fab: >100K LUTs with >500 MACs in TSMC16FFC -- this is our validation chip to prove out our new ELFX-2.5K Gen2 IP core. It uses GPIO but could be easily adapted for other signaling as required. We can do arrays from 100 to >100K LUTs, with MACs or not, with RAM or not and in multiple processes: TSMC16FFC/FF+, TSMC28HPM/HPC/HPC+, TSMC40ULP/LP are available now.
Click HERE for further information or contact us at firstname.lastname@example.org.
HARVARD SELECTS EFLX FOR DEEP LEARNING
Another Leader Adopts EFLX for Updating RTL in system at any time
Harvard University is a leader in Deep Learning research. You can see their recent ISSCC 2017 paper on their website here.
Harvard approached Flex Logix in February 2017 asking to use EFLX in their new deep learning chip. In deep learning, algorithms evolve quickly. By the time a hard-wired chip appears in silicon, the algorithms are already out of date, so the pace of learning is slowed. With embedded FPGA it is possible to implement some of the algorithms in reconfigurable logic so that algorithms can be updated and iterated in real time leading to a faster pace of innovation.
Harvard selected EFLX as the best embedded FPGA and because it was available in TSMC16FFC which they had selected for their next generation deep learning chip.
Deep Learning (also known as AI, artificial intelligence or machine learning) has applications in data centers, mobile and IoT and reconfigurable logic can improve these chips in each of these applications.
In less than 3 months Harvard was able to integrate a 10K LUT, 2x2 array of Gen2 EFLX-2.5K IP cores in TSMC16FFC (a mix of Logic and DSP) into their new deep learning chip which taped out in May 2017.
After evaluating their new chip, Harvard expects to publish their results, including the application and benefits of embedded FPGA, in a paper at a future conference.
The press release can be found HERE.
GEN 2 EFLX ARCHITECTURE AVAILABLE NOW IN TSMC 16FFC/FF+/12FFC
Flex Logix is just 3 years old but already has 4 EFLX ports to the 3 most popular foundry nodes: TSMC 40LP/ULP, TSMC 28HPM/HPC and now TSMC 16FFC/FF+/12FFC. And the TSMC 16FFC/FF+/12FFC ports are based on our new "Gen 2" architecture with substantial architectural improvements. As a result, we have the broadest, best and most scalable offering of embedded FPGA in the industry. And you will see more from us in future quarters.
The new EFLX-2.5K cores (Logic and DSP) available in TSMC 16FFC/FF+/12FFC feature the full Gen 2 Architecture with the following improvements:
- 6-input LUTs and an improved interconnect that result in ~20-30% fewer LUTs required and ~25% faster critical path performance for typical designs in the same process node compared to our "1st Gen" architecture
- MACs pipelined 10 in a row (versus 5 in "1st Gen") for higher performance for FIR/IIR filters and other DSP functions without needing to use the general interconnect network
- DFT enhancements to ensure >98% coverage of all stuck-at faults with much higher coverage possible with larger vector sets, provided by Flex Logix
- A parallel test configuration load mode that results in ~100x faster test times for Gen 2 versus Gen 1
- Readback circuitry that enables configuration bits to be checked for soft errors (and corrected) as frequently as desired to improve reliability for High-Rel applications like Automotive and Defense/Aerospace
See our TSMC16FFC/FF+/12FFC EFLX-2.5K/EFLX-100 web page for more details.
A validation chip is in fab now that has a maximum size 7x7 array of EFLX-2.5K DSP and Logic cores with >>100K LUTs and >500 MACs: high level GDS is shown to the right.
See our EFLX-100 validation chip for TSMC 16FF+ at DAC running >1GHz!
FLEX LOGIX RAISES $5M IN SERIES B FUNDING
See press release link HERE.
DARPA SELECTS EFLX
DARPA, the US government's Defense Advanced Research Projects Agency, has selected EFLX embedded FPGA and entered into an agreement for it to be made available to any company or government agency designing chips in TSMC® 16FFC for use by any branch of the US Government. Flex Logix has agreements with other organizations and companies, but DARPA is the first to be made public. Flex Logix EFLX-2.5K IP Cores in TSMC16FFC are available now.
See FLEX LOGIX™
in june at TSMC/YOKOHAMA,
In August at flash memory summit and at hot chips;
in september at tsmc Open Innovation platform;
& in october at arm techcon
See our events page for a detailed list of all events.
Follow us on Twitter @efpga or Linked-in for the latest news on Flex Logix.
Embedded FPGA for Architects & Physical Designers
Here is a link to the PDF of our keynote talk at REUSE2016: Embedded FPGA for Architects & Physical Designers.
Flexible, Proven Building Blocks: We Deliver More, Sooner
Our management team has the experience to grow Flex Logix rapidly while meeting commitments. Our engineers have worked at many of the world's best chip companies on processes from 180nm to 7nm designing high volume ICs. We can meet your needs and we will meet our commitments.
We prove our Hard IP in Silicon before you use it. We execute effectively and quickly: in 2.5 years we have designed EFLX™ in TSMC 40, 28 and 16FF. Our lead customers have their chips working with EFLX arrays embedded.
We will port to TSMC 22/55/65/90/180nm on demand. We can port to any CMOS process, foundry or captive, in ~6 months from receipt of PDK and standard cell library -- we only port with a committed customer to ensure we have a partner to help us optimize our digital architecture for the target process. For example, in 40ULP we optimized for numerous power management modes with rapid transitions, 0.5V state retention and even 0.5V operation if needed. Whereas in 16FF customers want performance, performance, performance. See EFLX Implementation Options for a full list. In all nodes it is the same digital architecture with the same programming software.
In each process node we implement up to 4 IP cores: EFLX-100 and EFLX-2.5K; each has an all-logic version and a version with embedded Multiplier-Accumulators for DSP Acceleration. Each IP core is a stand-alone FPGA, but incorporates additional top-level interconnect which allows automatic connection to adjacent IP cores turning them automatically into larger EFLX arrays.
Our innovative building block approach means we can deliver any size embedded FPGA from 100 LUTs to 100K LUTs, with about 75 sizes in between: and each size can be further customized with the mix of DSP acceleration and/or RAM that you might also need.
Our first two EFLX arrays have dual-4-input LUTs.
Our new "Gen 2" architecture, starting with TSMC 16, has 6-input LUTs with dual outputs/flip-flops; faster interconnect; fault coverage >>98%, 100x faster test times and more.
Join our other customers who are designing with EFLX embedded FPGA. Check out our Experience page.
Reconfigure your RTL in chip and in system whenever you want
Make one chip look like dozens: save the time and costs of multiple mask sets.
Allow your chip to be able to upgrade to handle new standards and specs: your chip will have a longer life and be more valuable.
We provide embedded FPGA to make this possible: any process, any size, optional DSP/RAM and programming software.
(Re)Configurable Clouds will change the world
Doug Burger, Microsoft talks about how the ability to reprogram a datacenter's hardware protocols (networking, storage, security) is a game changer: click here for his presentation at FPL2016.
EFLX™ embedded FPGAs give you the capability to implement reconfigurability in your Networking & Communications SoCs. We have EFLX available now in TSMC28HPM/HPC and very soon in TSMC16FF for your new designs.
Easy & More Powerful I/O Pin-Muxing
Most chips have pin mux-es. They are important but tedious and prone to human error. EFLX™ makes it easy AND fast to wire many more signals into the pin mux for great observability. The I/O Pin Mux can be reprogrammed at any time! Check out our IO Multiplexing page.
Extended Battery Life for IoT and Microcontrollers
Many times we hear "but FPGAs are high power" - maybe the chips are, but embedded FPGA can be very energy efficient. Tony Kozaczuk, our new Director of Solutions Architecture, has done an analysis showing that for the DSP functions he analyzed, a small EFLX array can take 2-5x less energy than an embedded processor (and that's before considering the energy for the ARM memory accesses), and executes faster as well. So an EFLX array can be used to do the repetitive DSP functions in a battery-backed chip, only waking up the processor for more complex tasks. See Tony's analysis on this page, with a link to the slide deck: set up a call with Tony to discuss your application: email email@example.com.
Flexible, Reconfigurable I/O for Microcontrollers & IoT
Tony Kozaczuk, Director of Solutions Architecture, joined us mid-2016 from Intel where he was Lead Systems Architect for multiple CPUs and before that an architect at Sun. He has now produced his 2nd application note showing how to connect EFLX™ to the APB bus and implement GPIO ports and serial interfaces in reconfigurable RTL, enabling one 40nm mask set to support dozens of different customers requested variations in GPIO/serial interfaces (and quickly). Check out the app note on this page: Flexible I/O.
UART, SPI & I2C Serial Interface IP Cores for EFLX
Most chip companies have their own RTL for the functions they want to program in embedded FPGA, but some have requested the availability of proven commercial IP from leading suppliers, especially for Serial Interface IP. Flex Logix has worked with CAST and SoC Solutions to qualify their UARTs, SPI and I2C Serial Interface Cores. The application note available on our Flexible I/O Page gives details of the LUT count and performance in TSMC® 40ULP for these IP cores.
EFLX™ for TSMC 40ULP in Validation
EFLX-100 Logic and DSP cores in multiple VT combinations are available now for integration in MCU, IOT and other ICs.
A validation chip will prove out all 10 versions of the EFLX-100 core: the validation chip is back, is fully functional and is being tested for performance over voltage ranges for the 10 versions and at temperature extremes. See our TSMC 40ULP page for information on the validation chip.
EFLX™ for TSMC 28HPM/HPC/HPC+ Proven in Silicon
TSMC 28 page here. Ask to see our validation report, under NDA.
EFLX™ Compiler - try it yourself!
Our software, the EFLX Compiler, converts your RTL into a bit stream which you load into the EFLX FPGA array to program it to run your RTL including DSP and Block RAM. The EFLX Compiler is in use at our lead customers and is now available for evaluation for qualified customers: contact us at firstname.lastname@example.org.
Need a summary to circulate to the team?
Download our 4-page PDF overview of our technology and company: click here to get the PDF.
Download our 2-page product brief on the EFLX-100 logic/DSP cores for TSMC 40ULP/LP: click here to get the PDF.
Download our 2-page product brief on the EFLX-2.5K logic/DSP cores for TSMC 28HPM/HPC/HPC+: click here to get the PDF.
Download our 2-page product brief on the EFLX-100 logic core for TSMC 16FF+/FFC/12FFC: click here to get the PDF
Download our 2-page product brief on the EFLX-2.5K logic/DSP cores for TSMC 16FF+/FFC/12FFC: click here to get the PDF.
Copyright © 2015-2017 Flex Logix Technologies, Inc. EFLX and Flex Logix are Trademarks of Flex Logix Technologies, Inc.