Flex Logix in EE Times’ Silicon 60 Class of 2018

EE Times list of 60 startups worth watching including Flex Logix: https://www.eetimes.com/document.asp?doc_id=1333985

Learn More about NMAX at the Edge AI Summit San Francisco Dec. 11

See the agenda HERE - a full day of talks on AI including the NMAX talk at 12noon with more technical information disclosure.

See HERE to register to attend.

Microprocessor Report: Flex Logix Spins Neural Accelerator

Download their article HERE.

NMAX™ Neural Inferencing: Fast, Low Latency, Low Cost, Low Power

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Cheng Wang “launched” NMAX October 31st with his talk at The Linley Processor Conference.

NMAX neural inferencing is:

  • modular from 1 to >100 TOPS

  • scalable: as you double the silicon area, you double the throughput in TOPS (it is throughput that matters)

  • low latency: NMAX loads weights fast, so performance at batch = 1 is usually as good as large batch sizes; this is critical for edge applications

  • low cost: NMAX has much higher MAC utilization than existing solutions. This means NMAX gets more throughput out of less silicon area

  • low power: NMAX uses on-chip SRAM very efficiently to generate high bandwidth so we need little DRAM. Less DRAM means lower cost and lower power.

See our NMAX page for much more information: click HERE.

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eFPGA Performance Modeling & Silicon Correlation

We generate timing for all process corners like you do for ASICs. See our slides from TSMC OIP HERE.

Boeing Licenses Flex Logix eFPGA for GF14LPP

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Beoing has licensed Flex Logix’ eFPGA for GlobalFoundries’ 14LPP process. GlobalFoundries manufactures 14LPP in Malta, near Albany, in upstate New York State. Boeing joins a growing list of companies designing with EFLX eFPGA. See the press release on our NEWS PAGE.

There are other Aerospace companies and US government organizations now designing or planning SoCs for GF14LPP using EFLX eFPGA. Get more information on EFLX eFPGA for GF14LPP HERE.

The availability of eFPGA on an advanced FinFET process manufactured in the USA is of major interest to US Aerospace companies who until now have not had access to American-manufactured FPGA technology. Market research reports show that almost 10% of FPGA sales by $ value are to Aerospace. And DARPA and others report that >30% of the IC content of Aerospace systems are FPGA. Integrating eFPGA enables SoCs to be made smaller, lighter, low power; and often integration breaks chip-to-chip I/O bottlenecks thus improving performance. Now eFPGA is available in an advanced FinFET process manufactured in the USA for those projects that require domestic manufacturing.

Flex Logix has been working for years with US Aerospace companies and government organizations: DARPA funded Flex Logix to demonstrate the viability of large, high performance eFPGA with a 200K LUT4 eFPGA evaluation chip on TSMC16FFC (which is available now on an evaluation board for customers to run their designs at GHz speeds). Sandia Labs contracted with Flex Logix to develop eFPGA for their proprietary 180nm wafer fab to develop multiple SoCs with eFPGA: the first SoC, Dragonfly, was described by Sandia at DAC 2018 (see below for slides) and that SoC is now out of fab and being validated.

Our support of US Aerospace companies does not limit our ability to support our customers worldwide: we have customers in Israel, China and other parts of Europe/Asia who are also benefiting from EFLX eFPGA. For customers in China who prefer domestic manufacture, EFLX eFPGA is available on multiple TSMC processes including 16FFC which is expected to be manufactured at TSMC’s Nanjing fab.

More Customers Have Working Silicon & Are in Design

Harvard and Sandia Labs both have working silicon using EFLX eFPGA and made presentations (DAC, HotChips); others have not made public disclosure. More customers are in design such as Boeing, HiPer, SiFive - other customers are in design but are not disclosing publicly at this time. See are Working Silicon Web Page for more details on these chips. More customers are in contract, planning and evaluation. The adoption of eFPGA has begun and is accelerating.

Harvard Silicon Shows eFPGA is Lowest Energy Flexible DNN

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Monday August 20, Harvard University presented a paper at Hot Chips: "SMIV: A 16nm SoC with Efficient and Flexible DNN Acceleration for Intelligent IoT Devices".  The design was done in TSMC16FFC.  They implemented several methods for neural network efficiency including a 2x2 array of EFLX eFPGA with two EFLX 4K Logic cores and two EFLX4K DSP cores with 40 22x22 MACs each for 80 total.  The best solution of four was AON which will not benefit from algorithm advances: there is a tradeoff between performance and future flexibility.  Of the more flexible solutions the eFPGA solution was similar in area efficiency to an ARM A53 and a quad-accelerator, but on energy efficiency the best of the flexible solutions by far is eFPGA (see chart at right).

Harvard's presentation is available to Hot Chips attendees and will be posted on the Hot Chips site in the future.

Harvard is working now on a follow-on neural accelerator using EFLX eFPGA again.

Working with Harvard, and with other customers, has helped us understand the needs for neural networks: on November 1st at the Linley Fall Process Conference we will unveil our Neural Inferencing Architecture called NMAX™. NMAX uses eFPGA for reconfigurable state machines and XFLX/ArrayLinx/RAMLinx interconnects for efficient and low power data movement. NMAX achieves scalable, high performance inferencing with very low DRAM bandwidth. Low DRAM bandwidth means fewer DRAMs, less DRAM $ and less power. See our NMAX page HERE on November 2nd for more details.

EFLX1K Core Architecture for 40-180nm Nodes
& for Fast Reconfigurable Control Logic in 7-28nm Nodes

Most applications in less advanced process nodes, from 40-180nm, do not need large arrays and want finer granularity: the EFLX 1K eFPGA core provides this.  This finer granularity for reconfigurable state machines is also of interest to customers in advanced nodes in 7-28nm nodes, especially in networking chips. The EFLX1K is available in both Logic and DSP versions, is fully compatible with EFLX Compiler, and can be implemented in any process node on customer demand in 6-8 months.

See our EFLX1K Page for more information and for a Target Specification.

Benchmarking eFPGAs: Performance, Area, Physical Design Issues

Flex Logix has now published an application note on benchmarking eFPGA performance showing details of performance with exact measurement conditions for a range of applications.  Unfortunately there is no competitive information but you can download the RTL files to use when you benchmark other eFPGA.  Go to the web page with the details HERE.

Also, there is public information from Achronix and Menta allowing a detailed comparison of area with Flex Logix on common process nodes. Go to the web page with the details HERE.

Tony Kozaczuk, Director Solutions Architecture, has written an article discussing all of these factors in benchmarking eFPGA: see HERE.for

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eFPGA Timing Signoff Methodology

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Click HERE for a video discussion by Senior VP Engineering Cheng Wang or HERE for a written summary.

 

EFLX Compiler Demonstration Video

Click on the image to the right for a ~10 minute video demo of EFLX Compiler.

 

 

 

EFLX200K 16nm Evaluation Board Demonstration Video

Click on the image to the right for a ~5 minute video demonstration.

 

 

EFLX4K eFPGA IP Core Validated on TSMC16FFC
EFLX200K Evaluation Boards Now Available

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The EFLX4K eFPGA IP core, both the Logic and DSP versions, have been fully validated on TSMC16FFC. The GDS is also compatible with TSMC16FF+ with no change, just retiming.

Evaluation boards are available now that integrate the EFLX200K validation chip (a 7x7 array of EFLX 4K cores: 182K LUT4, 560 MACs, 1.4Mbit attached SRAM, PLL & PVT) for customers to test their RTL on real silicon.  Customers can either use the boards at no cost for short-term evaluation or can purchase boards.  The evaluation board comes with documentation, examples, and test benches.

Contact info@flex-logix.com for more information on obtaining an evaluation board for evaluation or purchase.

RECOGNITION FOR FLEX LOGIX®

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Six Game Changer Companies to Watch in 2018: click HERE.
TSMC OIP Partner of the Year 2017: press release HERE.
Flex Logix joins TSMC IP Alliance: press release HERE.
EE Times Top 60 to Watch : SEE HERE.

Follow us on Twitter @efpga or Linked-in for the latest news on Flex Logix.

 

Flexible, Proven Building Blocks: We Deliver More, Sooner 

Our management team has the experience to grow Flex Logix rapidly while meeting commitments.  Our engineers have worked at many of the world's best chip companies on processes from 180nm to 7nm designing high volume ICs.  We can meet your needs and we will meet our commitments.  

We prove our Hard IP in Silicon before you use it.  We execute effectively and quickly: in 2.5 years we have designed EFLX™ in TSMC 40, 28 and 16FF.  Our lead customers have their chips working with EFLX arrays embedded.

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We will port to TSMC 7/22/55/65/90/180nm on demand.  We can port to any CMOS process, foundry or captive, in ~6 months from receipt of PDK and standard cell library -- we only port with a committed customer to ensure we have a partner to help us optimize our digital architecture for the target process.  For example, in 40ULP we optimized for numerous power management modes with rapid transitions, 0.5V state retention and even 0.5V operation if needed.  Whereas in 16FF customers want performance, performance, performance.  See EFLX Implementation Options for a full list. In all nodes it is the same digital architecture with the same programming software.

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In each process node we implement up to 4 IP cores: EFLX150 and EFLX4K; each has an all-logic version and a version with embedded Multiplier-Accumulators for DSP Acceleration.  Each IP core is a stand-alone FPGA, but incorporates additional top-level interconnect which allows automatic connection to adjacent IP cores turning them automatically into larger EFLX arrays.

Our innovative building block approach means we can deliver any size embedded FPGA from 100 LUTs to 200K LUT4s, with about 75 sizes in between: and each size can be further customized with the mix of DSP acceleration and/or RAM that you might also need.  We have even fabricated an EFLX200K array which is in characterization now.

IF 200K LUTs is too small for you, inquire about our roadmap to ~800K LUT4 arrays which we can implement quickly: info@flex-logix.com.

EFLX® Compiler - try it yourself!

Our software, the EFLX Compiler,  converts your RTL into a bit stream which you load into the EFLX FPGA array to program it to run your RTL including DSP and Block RAM.  A GUI is available for many phases of eFPGA design, timing, I/O placement and more.  The EFLX Compiler is in use at our lead customers and is now available for evaluation for qualified customers: contact us at info@flex-logix.com.

Learn more about EFLX Compiler here.

Need a summary to circulate to the team?

Download our 4-page PDF overview of NMAX neural inferencing: click here to get the PDF.

Download our 4-page PDF overview of EFLX eFPGA:  click here to get the PDF.
Download our 2-page product brief on the EFLX100 logic/DSP cores for TSMC 40ULP/LP: click here to get the PDF.
Download our 2-page product brief on the EFLX4K logic/DSP cores for TSMC 28HPC/HPC+: click here to get the PDF.
Download our 2-page product brief on the EFLX150 logic core for TSMC 16FF+/FFC/12FFC: click here to get the PDF
Download our 2-page product brief on the EFLX4K logic/DSP cores for TSMC 16FF+/FFC/12FFC: click here to get the PDF.
Download our 2-page target spec on the EFLX4K logic/DSP cores for GF 14LPP:  click here to get the PDF.

Download our 2-page DSP Architecture brief: click here to get the PDF.

Copyright © 2015-2018 Flex Logix Technologies, Inc. EFLX and Flex Logix are Registered Trademarks of Flex Logix Technologies, Inc.  
NMAX, ArrayLinx, RAMLinx and XFLX are Trademarks of Flex Logix Technologies, Inc.