Acceleration for SoCs, MCUs, DataCenters & more

Every chip has one or more ARM/ARC/MIPS/... processors executing code.

For tasks that occupy much of the processor bandwidth, an accelerator in hardware can often process the task in much less time. (Of course, the accelerator doesn't replace the processor, just accelerates the most work-intensive task).

But if you use a hard-wired accelerator, only one task can be accelerated.

Making the accelerator reconfigurable makes it possible to accelerate multiple tasks, as the workload requires or as different customers/applications demand. Acceleration of 40-140x is achievable in the examples studied in our application note (see below).

Embedded FPGA is now available on the most popular process nodes and in any size, and with optional MACs/RAM, to provide reconfigurable acceleration from MCUs to DataCenters.

We even have an evaluation board that implements the Flexible Micro architecture with customer-programmable eFPGA: SEE HERE.

Tony Kozaczuk, Flex Logix' Director of Architecture Solutions has  generated an application note on AXI/Accelerators  which details how to connect embedded FPGA to AXI and AHB buses and shows several examples of reconfigurable accelerators, giving area and performance (in 16nm - contact us for 28nm or other process nodes) and showing how much faster the embedded FPGA accelerators are than a typical ARM processor (we use ARM because it is by far the most popular processor). Look at the bottom of this page for downloadable files for the Verilog in the app note.

Tony would be happy to talk to you about your application: contact him at info@flex-logix.com. Tony was previously a Lead Systems Architect on several Intel CPUs and before that an architect at Sun, so he can see the problem from your perspective.

Verilog files for AXI/AHB/Accelerators App Note:

Bus interfaces:

AHBmaster_wrapper_tb.v
AHBmaster_wrapper.v
APBslave_wrapper_tb.v
APBslave_wrapper.v
AXI_master_slave_wrapper_tb.v
AXImaster_wrapper.v
AXIslave_wrapper.v

Accelerators:

AES_cipher_top.v
FFT256_spiral.v
JPEG Encoder VHDL Files.zip
SHA256.v