RAM of any size and kind in your EFLX™ array

Many applications like DSP benefit from blocks of RAM distributed in the array.

Each EFLX-2.5K core has >1000 I/O's.  When multiple cores are arrayed, the I/O's that face inward are available to control block RAM using our patented architecture.

Any amount and kind of RAM can be inserted between cores: single or dual port, x16/x32/x64/..., ECC/parity/neither, and optional MBIST.  The EFLX compiler can map your RTL onto the BRAM you want to configure in the EFLX array (and to BRAM external to the array).

A specific example show below is a 2x2 EFLX array with 10K LUTs integrating 576Kbits of dual port RAM and 288Kbits of single port RAM.  In this example the RAM adds 20% to the total array size. Many variations are possible.  Contact us to discuss your specific requirements.