RAM of any size and kind in your EFLX™ array
(or customer accelerator logic)
Many applications like DSP benefit from blocks of RAM distributed in the array.
Of course it is possible to attach RAM to the external I/O pins of the array.
You can also have array embedded within the array! Each EFLX4K core has >1000 I/O's. When multiple cores are arrayed, the I/O's that face inward are available to control block any kind of RAM.
Any amount and kind of RAM can be inserted between cores: single or dual port, x16/x32/x64/..., ECC/parity/neither, and optional MBIST. The EFLX compiler can map your RTL onto the RAM you want to configure in the EFLX array (and to RAM external to the array).
A specific example show below is a 2x2 EFLX array with 16K LUTs integrating 576Kbits of dual port RAM and 288Kbits of single port RAM. In this example the RAM adds 20% to the total array size. Many variations are possible. Contact us to discuss your specific requirements.
We can do the same thing with custom accelerators, say matrix multipliers or floating point, and the EFLX Compiler can provide software support for them.