One is in Fab now

2.5D multi-chip packaging, mounting bumped die on interposers, is becoming increasingly popular and cost effective.

In some cases, a customer may prefer to have EFLX FPGA in the form of a chipset: a bumped die that is primarily FPGA with interface circuitry, as specified by the customer, to attach to another die via the interposer.

Flex Logix has already designed such a chip: our validation chip for our >100K LUT, >500 MAC EFLX array in TSMC16FFC which is in fab now.  The signaling on this chip is GPIO but could be easily changed to much higher speed die-to-die signaling over an interposer.

Our IP comes in sizes from 100 LUTS to >100K LUTs with options for MACs and RAM and is now available for TSMC40ULP/LP, TSMC28HPM/HPC/HPC+ and TSMC16FF+/FFC.  EFLX is also being ported to other process nodes based on customer demand.

Ask us for more information:  email info@flex-logix.com and mention chiplets.  



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