EFLX FPGA CAN BE DELIVERED FOR CHIPLETS
Use to provide AXI Accelerator for ASICs/SoCs
2.5D multi-chip packaging is becoming increasingly popular and cost effective.
When cost reducing an FPGA to an ASIC, you can now keep some of the ASIC flexible/reconfigurable.
Your FPGA is in 28nm or 16nm processes, but. your cost reduced ASIC is in 65/90/110nm. We can provide EFLX on these processes but performance will be less.
If you want 28nm or 16nm FPGA performance for your ASIC, we can provide a Chiplet with >200 I/O with 200-400MHz CMOS signaling to enable implementation of an AXI interface to provide a reconfigurable accelerator for your ASIC.
Ask us for more information: email firstname.lastname@example.org and mention chiplets.
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