Even a single EFLX™ 2.5K core has >1000 high speed I/O.
EFLX embedded FPGA can be integrated in a chip in many ways: here are 3 common examples.
EFLX can act as an reconfigurable accelerator or customizable logic block on your processor bus. Flex Logix can provide the RTL for connecting to various ARM buses.
EFLX can be in your control or data path (for best performance, use the EFLX-100 core). EFLX has hundreds to thousands of interconnects, so you can connect to very wide data paths.
EFLX I/O can be connected to RAM (and the EFLX Compiler will control it), GPIO, PHYs, A/D, D/A.
Combinations of these examples are of course possible as well.
The EFLX array has clock trees and clock de-skew for up to 8 clocks.
Power management is available for minimizing static power when the EFLX array is not in use.
Flex Logix uses Voltus® and Apache® to determine IR drop for worst case operating conditions and worst case RTL patterns with high switching factors.
To integrate the EFLX array into your SoC, Flex Logix will provide GDS, LEF, LIB, CL, Verilog, AXI RTL, configuration interface RTL and extensive documentation: data sheets, DSP block user's guide, power management, DFT/ATPG, configuration guidelines & power bus interfacing. And we work with you from start to finish to ensure your SoC is successful.