GEOFF TATE. CEO. Originally from Edmonton, Canada. BSc, Computer Science, University of Alberta. MBA Harvard. MSEE (coursework), Santa Clara University. 1979-1990 AMD, Senior VP, Microprocessors and Logic with >500 direct reports. 1990 joined 2 PhD founders as founding CEO to grow Rambus from 4 people to IPO to $2 Billion market cap, till 2005. Lead Director of Everspin, the leading MRAM company.
CHENG WANG. Senior VP Engineering: Architecture, Software, Silicon. Originally from Shanghai, PRC. BSEECS, UC Berkeley. Two years as VLSI designer at Zoran. MSEE, EE PhD UCLA: designed 5 FPGA chips from 90nm to 40nm. 2013 Distinguished PhD Dissertation Award. 2014 ISSCC Lewis Winner Award for Outstanding Paper. Multiple patents at UCLA and Flex Logix.
ANDY JAROS. VP Sales. Originally from Scottsdale, AZ. BS Chemical Engineering, Arizona State University. Over 20 years of sales and sales management experience starting as Account Sales Manager at Motorola for Apple, Sun, SGI then Director Strategic Accounts at ARM. Moved to ARC as VP Sales, North America. When Virage acquired ARC, became VP Global Accounts and lead worldwide sales effort for ARC. When Synopsys acquired Virage, was interim VP Worldwide Sales for Virage/ARC, then transitioned into Director of Product Solution Sales coordinating all ARC sales activities for Synopsys in North America. During Andy’s time selling ARC, it became the #2 embedded processor by unit market share.
ABHIJIT ABHYANKAR. VP Silicon Engineering. Originally from Pune, India. BSEE University of Utah. MSEE Stanford. MBA San Jose State. Over 20 years experience in silicon and system design at LTX then Rambus where he was Senior Engineering Director and Technical Director. Has managed over 100 people in high speed digital logic, mixed signal, system, verification and software teams. His projects have resulted in millions of chips and systems sold by companies such as Intel, Sony, IBM, Toshiba and others.
TONY KOZACZUK: Director of Solutions Architecture. Originally from Buenos Aires, Argentina. BSEE San Francisco State University. Tony's team's role at Flex Logix is to provide support to customers to evaluate architectural alternatives for using EFLX to achieve the best result. Over twenty years Architecting systems and ICs at National, Sun and Intel. Most recently at Intel, Tony was Lead System Architect for multiple generations of Intel CPU Cores, and led system clocking architecture for all client systems. At Sun, Tony was Lead System Architect for several servers and workstations and led I/O architecture and microarchitecture of several systems and chips.
FAN MO. Technical Director of FPGA CAD Software Development. Originally from Shanghai, PRC. BSEE & MSEE, Fudan University. PhD EE/CS, University of California, Berkeley researching novel placement and routing algorithms. Over a dozen years working on FPGA and Structured ASIC synthesis, placement and routing first at Synplicity (Synplify) then at Synopsys when they acquired Synplicity. He has worked on high-performance place & route for many generations of Virtex FPGAs, timing-driven large-scale placement algorithms and global routing algorithms.
VALY OSSMAN. Technical Director of Solutions Architecture. Valy brings more than 20 years of experience in networking and chip architecture. Originally from Romania, Valy grew up in Israel and attended Ben Gurion University for his BSc in EE then worked at Galileo (now Marvell), Cisco and Siliquent (now Broadcom) before co-founding Tehuti Networks. Later, Valy joined Passave (acquired by PMC) working on fiber-to-home optical communications SoCs as a systems architect then as part of the CTO Office of PMC when he relocated to Silicon Valley. Valy was also senior group director of FPGA prototyping platforms at Cadence where he managed the R&D and customer support teams.
APARNA RAMACHANDRAN. Senior Hardware Manager, Silicon Engineering. Originally from Chennai, India. BSEE, University Madras & MSEE, Arizona State University. MTS, Principal Engineer then Sr Hardware Design Manager at Sun/Oracle with >15 years design experience and >5 years management experience in process technologies from 130nm to 7nm.
FANG-LI YUAN. Hardware Design Manager, Silicon Engineering. Originally from Taoyuan, Taiwan. BSEE, MSEE National Taiwan University. EE PhD UCLA: with Cheng Wang designed 5 FPGAs from 90nm to 40nm. Project lead on two EFLX4K ports. 2014 Distinguished PhD Award. 2014 ISSCC Lewis Winner Award for Outstanding Paper.
DEJAN MARKOVIC. Technical Advisor. Originally from Pozega, Serbia. Professor of EE at UCLA: PhD Supervisor of Cheng Wang and Fang-Li Yuan. 2007 D. Sakrison Memorial Prize, 2009 NSF Career Award, 2010 ISSCC Jack Raper Award. 2014 ISSCC Lewis Winner Award for Outstanding Paper.