We have delivered our Gen 2 EFLX IP Core for Sandia National Laboratories' proprietary 180nm process for for their own wafer fab. We can do the same for your fab/process node.
All new EFLX "ports" (implementations in new process nodes) will feature the new Gen 2 EFLX architecture: 6-input LUTs (or dual 5-input LUT) and improved interconnect (higher performance) and DFT features same as are incorporated in the new EFLX cores in TSMC 16FFC/FF+, TSMC 28HPC/HPC+ and Sandia's 180nm process. All share the same digital architecture and are programmed by the EFLX Compiler, but we can optimize the circuit implementation for your needs.
EFLX IP Core Architecture Options
In doing a new EFLX port to a new process node, there are many choices/options to be considered:
We can implement one or all of EFLX1K/Logic, EFLX1K/DSP, EFLX4K/Logic, EFLX4K/DSP
We can optimize certain features that may be important for certain specialized applications: for example, we can increase the I/O count or increase the number of MACs in the DSP core
We can vary the width of the configuration load port to provide faster configuration loads for operation and/or for test
We can provide RTL to connect the EFLX Array to JTAG and standard buses like APB, AHB and AXI
At the Array level, we can integrate any kind of RAM, using foundry-provided memory compilers: the # ports, width, depth, number you wish with parity or ECC or neither
EFLX IP Core Circuit Design Options
Our design is all digital based on the PDK and the foundry-provided standard cell library for the process. There are many options or tradeoffs in the circuit implementation of the chosen digital architecture:
If a process node's PDK/standard cells support multiple voltage ranges, we can design the EFLX IP to be optimized for one of them OR to be able to be used with all of them (IR Drop and power-bussing is done to be sufficient for the highest performance option)
We can design to support the full temperature range supported by the PDK/standard cells or a subset or both
We can design to support one Vt mask combination or all possible Vt mask combinations (IR drop and power-bussing is done to be sufficient for the highest performance option) -- typically there are two Vt masks available: the configuration-bits are implemented with the lower-power Vt to minimize power; the logic involved in the critical path is implemented in the high-power Vt
We can generate LIB files with as many process corners as requested and supported by the PDK/standard cells
We can implement a Rad-Hard EFLX embedded FPGA if given a Rad-Hard standard cell library (attention also has to be given to clocks, etc.) - this very valuable for Space applications
Power Management Options
Power Management versus Performance: at one extreme some applications want maximum performance in "always on" applications (Networking, Base Stations); at the other extreme applications want reasonable performance at low power with options and modes to minimize power quickly in "quiet periods" with fast return to full speed operation.
Maximum power-management features existing in the EFLX IP core in TSMC 40U
The portion the EFLX core which is not performance sensitive is not power-gated so that configuration state is retained; also, for TSMC 40ULP the state of the flip flops in the RBB cells are retained when power gated so that the core can be power gated BETWEEN clocks!
The configuration bits and flip flops are designed to retain state down to 0.5V for a deep sleep option below Vdd(min)
The Vss and VBP/VBN can be controlled by the rest of the chip to allow further power management as desired
The times to transition between power management states has been made quite short both turning downing/off and turning up/on
There is a middle-ground for power-management such as implemented in the EFLX core in TSMC 28HPM/HPC. There is power-gating but not for cycle-by-cycle power-gating and without the Vss/VBP/VBN control.
In TSMC16FF+/16FFC the applications at this time are "always on" and want maximum performance (~1GHz for single-stage, wide-logic-cone RTL). Maximum performance is achieved with a larger IR drop budget: power-gating uses part of the IR drop budget, so not having power-gating means higher frequencies can be obtained. Of course, power buses in the core are increased appropriately (we simulate all IP cores for worst case PVT conditions with >90% utilization RTL with maximum switching rates, so that your code will run with confidence).
If the port is to a mainstream Foundry, Flex Logix will typically design, fabricate and characterize a Validation Chip over voltage and temperature with worst-case, high utilization test RTL to verify that all specifications are met. Our Validation Chips have on-chip PLL to ensure precise clocks and clock rates that allow maximum performance testing and have on-chip PVT monitors to ensure measurements are done at worst case junction voltages and temperatures.
If the port is to a proprietary Fab process, Flex Logix can design the Validation Chip or the customer may wish to do so.
Implementation Time for a new EFLX IP Core
Once we have the PDK, standard cells and the engineering team is available, implementation time is about 6-8 months to delivery of all design deliverables and tape-out of a validation chip. Remember to allow time for evaluation and contract negotiation.