NEW "Gen 2" Architecture for EFLX in TSMC 16/12
Gen 2 architecture raises the bar on performance and density
The EFLX150 Logic Core and EFLX4K Logic and DSP cores in TSMC 16FF+/FFC/12FFC use our latest "Gen 2" architecture with the following improvements (ALL future EFLX implementations will also be "Gen 2"):
- Improved, higher performance interconnect, especially for larger arrays
- 6-input LUTs with Dual Outputs with 2 optional flip flops (can also be dual 5-input LUTs) - higher logic density and higher performance due to fewer LUT stages
- The Gen 2 combination of the improved interconnect and wider LUTs results in ~20-30% reduction in LUTs required and ~25% improvement in critical path performance compared to the first generation dual-4-input-LUTs in the same process node. A LUT6 has 1.6x the logic capacity of a single LUT4. Read here why 6-input LUTs give higher performance and higher density.
- In the EFLX-2.5K DSP cores, the MACs are pipelined 10 in a row (compared to 5 in Gen 1) enabling higher performance for FIR/IIR filters, etc by using high speed data pipelining rather than using the general programmable interconnect network
- DFT is enhanced to provide >98% coverage of all stuck-at faults with significantly higher coverage achieved with larger test vector sets, which Flex Logix provides.
- Test time for the Gen 2 architecture is enhanced with new parallel load logic which reduces test time by ~100x compared to the first generation
- Readback circuitry (EFLX4K TSMC 16FFC/FF+ and all future implementations) enables configuration bits to be read back and checked for soft errors (and corrected) as frequently as desired to improve reliability for High-Rel applications like automotive and defense/aerospace
EFLX4K for TSMC 16FFC/FF+/12FFC is available now and a Validation Chip (16FFC) is in test; Evaluation Boards will be available in Q4
The EFLX4K Logic Core and DSP core are both available now: GDS, Verilog, etc etc.
Licensees have already taped-out chips using EFLX Arrays based on the new EFLX4K TSMC16FFC IP core, which is also compatible with TSMC 16FF+ and TSMC 12FFC (timing will need to be rechecked at all process corners).
Here is a product brief you can distribute to your team/customers: Gen2 EFLX4K TSMC16FFC/FF+/12FFC Product Brief.
The EFLX4K cores in TSMC 16/12 use just 7 layers of metal (M1+ 2Xa_1Xd_h_3Xe_vhv) making them compatible with essentially all TSMC 16/12 metal stacks.
The EFLX4K cores are interchangeable in arrays and measure 1.0 sq mm in area. Arrays of any rectangular size from 1x1 to 7x7 are possible enabling ~50 array sizes up to 200K LUTs to meet all customer needs. Array level performance for RTL will vary primarily with the number of logic levels and the length of critical paths, but performance of well design RTL should be >500MHz (well designed means pipelining designs for FPGA architecture, not just dropping in an RTL optimized for an ASIC with 30+ logic stages).
The density of TSMC16/12 EFLX4K cores in LUTs/square millimeters is very high and is similar to the Intel Stratix 14nm FPGA described at ISSCC 2017.
The EFLX4K cores operate over all nominal voltages supported by TSMC 16FFC/FF+/12FFC and over -40C Tj to +125Tj.
The cores have been verified with high speed "stress" RTL like 100% utilization inverter chains to ensure that high speed, high switching factor RTL can operate at max performance within IR drop budgets.
A detailed data sheet with extensive specifications and operation details is available under NDA. Here is a block diagram of the EFLX4K IP core.
The EFLX4K IP cores are being validated in a validation chip with a 7x7 EFLX200K array consisting of 14 EFLX4K DSP cores and 35 EFLX4K Logic cores: ~170K LUT4s and 560 MACs; the validation chip also has numerous banks of high speed RAM, a PLL for >1GHz operation and PVT monitors to determine exact on-chip Tj and Vj for validation of specs at worst case conditions.
The validation chip is in fab. When silicon is received it will also be used to produce evaluation boards to enable customers to try actual RTL on actual silicon of designs of very large sizes.
A high level GDS plot of the validation chip is shown to the right.
The chip is functional and validation is in progress.
EFLX150 for TSMC® 16FF+/FFC/12FFC is available now and Silicon is Fully Validated
EFLX150 in TSMC 16FF+/FFC enables programmable networking chips with wide, reconfigurable logic from 150 to 3.7K LUT4s running ~1GHz (exact speed depends on the RTL and the voltage range).
The EFLX150 core in TSMC 16FF+/FFC has been enhanced to provide higher performance for the wide logic cones of network control logic:
- 96 each of 6-input LUTs (also useable as dual 5-input LUTs & equivalent to ~150 LUT4s): wider LUTs mean wide logic cones can be handled in fewer stages meaning higher performance and higher density. Read here why we switch to 6-LUTs for speed and density.
- 224 inputs and 224 output: more inputs means wider logic paths can be handled in fewer EFLX150 cores
All voltage ranges are supported for 16FF+ and 16FFC over the full -40 to 125C temperature range.
A single EFLX150 core is 0.05 mm2 in size. It uses just 6 metal layers (M1+2Xa_1Xd_h_2Xe_vh) so it is compatible with almost all FF+/FFC metal stacks.
The EFLX150 core tiles in ~25 array sizes from 150 to 3.7K LUTs.
TRY OUT YOUR RTL: get a software evaluation license for the EFLX Compiler with worst-case timing files for EFLX150 in TSMC 16FF+/FFC to see how your RTL performs and how many LUTs it uses. Email firstname.lastname@example.org to arrange your license.
Here is the TSMC 16FF+/FFC EFLX150 core product brief.
A much more detailed data sheet is available under NDA: contact us at email@example.com.
The validation chip includes two array sizes and checks out the circuitry for "tiling" into larger arrays. An on-chip PLL enables generating clocks >1GHz. On-chip SRAM provides a "tester on a chip" to enable >1GHz operation at worst case conditions to verify performance versus simulation. On-chip Process/Voltage/Temperature monitors ensure testing is being done at worst case conditions on-die. Validation is complete and a detailed report is available under NDA: firstname.lastname@example.org.