Flex Logix utilizes a new breakthrough interconnect architecture: less than half the silicon area of traditional mesh interconnect, fewer metal layers, higher utilization and higher performance. The ISSCC 2014 paper detailing this technology won the ISSCC Lewis Winner Award for Outstanding Paper. Previous recent winners of this top award include Nvidia, Bosch, Sandisk and Toshiba.
Customers want a silicon proven solution at low cost. But customers want different numbers of LUTs. Flex Logix innovation allows our EFLX-2.5K core and EFLX-100 core to be easily and quickly arrayed, without any GDS changes, from a 1x1 array to a 7x7 array (5x5 for EFLX-100).
SUPERIOR LOW-POWER DESIGN METHODOLOGY
EFLX cores can be power gated to reduce power demand for different applications.
MULTIPLE CLOCK DOMAINS AT LOW SKEW
Each EFLX core can have two clock domains and the array can have up to 8 total, all with low skew.
RAM OF ANY KIND/SIZE
We can provide the exact kind and amount of RAM you need integrated in your EFLX array.
Our EFLX compiler is fully operational, proven with our silicon, and working at multiple customers.
Multiple US and international patent applications cover various aspects of our innovative technology and implementations. Our issued US patents include:
US Patent 9,240,791 Clock Distribution Architecture for Logic Tiles of an Integrated Circuit and Method of Operation Thereof
US Patent 9,496,876 Clock Distribution Architecture for Logic Tiles of an Integrated Circuit and Method of Operation Thereof
US Patent 9,503,092 Mixed-Radix and/or Mixed-Mode Switch Matrix Architecture and Integrated Circuit, and Method of Operating Same
US Patent 9,543,958 Multiplexer-Memory Cell Circuit, Layout Thereof and Method Manufacturing Same